公开(公告)号：US20140132873A1

公开(公告)日：2014-05-15

申请号：US14232407

申请日：2012-07-09

Applicant: Isao Ogasawara ,  Masahiro Yoshida

Inventor： Isao Ogasawara ,  Masahiro Yoshida

IPC: G02F1/13

CPC classification number: G02F1/1309 ,  G02F1/13306 ,  G02F1/13452 ,  G02F2001/13456 ,  G02F2201/506 ,  G02F2201/508

Abstract: An active matrix display device has: a first auxiliary wiring line (700); a second auxiliary wiring line (710) positioned outside of a plurality of second lead-out wiring lines (250) and a first driver circuit in a plan view; and an external auxiliary wiring line (790). Along each of a plurality of connecting wirings (900) are disconnected portions (91) inhibiting electrical connections between a plurality of transmission terminals and first common wiring lines (130). A plurality of intersections (901), where the first auxiliary wiring line (700) and the plurality of connecting wirings (900) intersect, are positioned more to the side of the plurality of transmission terminals than to the disconnected portions (91) in each of the plurality of connecting wiring lines (900).

Abstract translation: 有源矩阵显示装置具有：第一辅助布线（700）; 位于多个第二引出布线（250）外侧的第二辅助布线（710）和俯视图中的第一驱动电路; 和外部辅助布线（790）。 沿着多个连接配线（900）中的每一个是断开多个发送端子和第一公共布线（130）之间的电连接的断开部分（91）。 在第一辅助配线（700）和多个连接配线（900）相交的多个交叉点（901）比各断路部分（91）位于多个发送端子的侧面 的多个连接布线（900）。

公开(公告)号：US08723845B2

公开(公告)日：2014-05-13

申请号：US13574049

申请日：2010-11-26

Applicant: Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi

Inventor： Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada ,  Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi

IPC: G06F3/038

CPC classification number: G09G3/3688 ,  G09G2300/0413 ,  G09G2310/0297 ,  G09G2330/08 ,  H01L27/12 ,  H01L27/124 ,  H01L29/41733

Abstract: A signal distribution circuit (3) includes (i) a redundancy TFT element (8) provided so as to have a channel width identical to those of driving TFT elements (7), (ii) first redundancy lines (9a, 9b), (iii) a second redundancy line (10), and (iv) a third redundancy line (11). It is therefore possible to provide a liquid crystal display device including the signal distribution circuit (3) in which, even in a case where a leaking part (a defect part) is generated in any of the driving TFT elements (7), it does not take long to restore the leaking part, and productivity can be improved, the driving TFT elements (7) keeping respective channel widths identical to one another even after the leaking part is restored.

Abstract translation: 信号分配电路（3）包括（i）设置为具有与驱动TFT元件（7）相同的沟道宽度的冗余TFT元件（8），（ii）第一冗余线（9a，9b），（ iii）第二冗余线（10），和（iv）第三冗余线（11）。 因此，可以提供一种包括信号分配电路（3）的液晶显示装置，其中即使在任何驱动TFT元件（7）中产生泄漏部分（缺陷部分）的情况下，也可以 即使在泄漏部分恢复之后，驱动TFT元件（7）保持各个通道宽度彼此相同，也不会耗费时间来恢复泄漏部分，并且可以提高生产率。

公开(公告)号：US08686980B2

公开(公告)日：2014-04-01

申请号：US13521308

申请日：2010-12-01

Applicant: Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

Inventor： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC: G06F3/038 ,  G09G5/00

CPC classification number: G02F1/13454 ,  G02F1/13458 ,  G02F2001/136263 ,  H01L27/124

Abstract: A gate driving circuit (60) separated into a plurality of stages (ST) is provided. In each of the stages (ST), TFT elements (T1) through (T4) are provided, branch lines (78) that connect clock lines (72, 74) to the TFT elements are provided. Junction lines (79A, 79B) are each extended from the branch line (78A) of interest to electrically connect the branch line (78A) of interest to the TFT elements (T2, T4) provided in the stage (ST(j)) different from the stage (ST (j−1)) where the TFT elements (T1, T3) connected to the branch line (78A) of interest are provided.

Abstract translation: 提供分离为多个级（ST）的栅极驱动电路（60）。 在各级（ST）中，设置TFT元件（T1）至（T4），将时钟线（72,74）连接到TFT元件的支线（78）设置。 各接线（79A，79B）各自从感兴趣的支线（78A）延伸，将感兴趣的分支线（78A）电连接到设置在台（ST（j））中的TFT元件（T2，T4）不同 提供与感兴趣的分支线路（78A）连接的TFT元件（T1，T3）的级（ST（j-1））。

公开(公告)号：US20130039455A1

公开(公告)日：2013-02-14

申请号：US13642714

申请日：2011-01-21

Applicant: Satoshi Horiuchi ,  Masahiro Yoshida ,  Takaharu Yamada ,  Isao Ogasawara ,  Shinya Tanaka ,  Tetsuo Kikuchi

Inventor： Satoshi Horiuchi ,  Masahiro Yoshida ,  Takaharu Yamada ,  Isao Ogasawara ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC: G11C19/18

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: A shift register stage includes a first transistor having a capacitor electrode (CAPm) that faces, in a film thickness direction, at least one of source and drain electrodes (Tr4s and Tr4d) of the first transistor in a side opposite to a gate electrode (Tr4g) of the first transistor. One of (i) the capacitor electrode (CAPm) and (ii) the one of the source and drain electrodes (Tr4s and Tr4d) which faces the capacitor electrode (CAPm), is electrically connected to a control electrode of an output transistor of the shift register stage.

Abstract translation: 移位寄存器级包括具有电容器电极（CAPm）的第一晶体管，其在膜厚度方向上与第一晶体管的与栅电极相反的一侧中的至少一个源电极和漏电极（Tr4s和Tr4d） Tr4g）的第一晶体管。 （i）电容器电极（CAPm）和（ii）面对电容器电极（CAPm）的源极和漏极（Tr4s和Tr4d）中的一个电连接到输出晶体管的控制电极 移位寄存器阶段。

公开(公告)号：US20130038583A1

公开(公告)日：2013-02-14

申请号：US13642894

申请日：2011-01-28

Applicant: Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

Inventor： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

IPC: G11C19/00 ,  G06F3/038 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3677

Abstract: Provided is a shift register circuit which includes: first through N-th circuit sections (1a, 1b) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR1, SR2, . . . , SRn) are connected in cascade; and supply wires (10b, 10c, 10e, 10f). Each of the first through N-th circuit sections (1a, 1b) receives drive signals (CKA1, CKA2, CKB1, CKB2) for driving the shift register stages (SR1, SR2, . . . , SRn) via supply wires (10b, 10c, 10e, 10f) exclusive for the each of the first through N-th circuit sections (1a, 1b).

Abstract translation: 提供一种移位寄存器电路，其包括：第一至第N电路部分（1a，1b）（N是等于或大于2的整数），其中每个电路部分中的多个移位寄存器级（SR1，SR2，...， 。，SRn）级联连接; 和电源线（10b，10c，10e，10f）。 第一至第N电路部分（1a，1b）中的每一个接收用于驱动移位寄存器级（SR1，SR2，...，SRn）的驱动信号（CKA1，CKA2，CKB1，CKB2） 10c，10e，10f）分别用于第一至第N电路部分（1a，1b）。

公开(公告)号：US20110298484A1

公开(公告)日：2011-12-08

申请号：US13138421

申请日：2009-11-19

Applicant: Nobuyuki Kawase ,  Isao Ogasawara ,  Kazuhide Ikuta

Inventor： Nobuyuki Kawase ,  Isao Ogasawara ,  Kazuhide Ikuta

IPC: G01R31/3187

CPC classification number: G01R31/026 ,  H05K1/0268 ,  H05K1/18 ,  H05K2201/09227

Abstract: An electronic circuit of at least one embodiment of the present invention includes: a plurality of electronic parts, of the plurality of electronic parts, at least one electronic part being at least one main part and the other electronic parts being auxiliary parts, the at least one main part being necessary for determination of whether or not the electronic circuit operates normally, the auxiliary parts being unnecessary for determination of whether or not the electronic circuit operates normally, the auxiliary parts being connected to a line which is connected to the at least one main part so as to supply a signal necessary for operation of the at least one main part or output a signal obtained by the operation of the at least one main part. This provides an electronic circuit which is capable of properly detecting a circuit wiring disconnection and easily detecting faulty wiring between elements without the need of providing the electronic circuit with more components for detecting a circuit wiring disconnection.

Abstract translation: 本发明的至少一个实施例的电子电路包括：多个电子部件中的多个电子部件，至少一个电子部件是至少一个主要部件，而另一个电子部件是辅助部件，至少 确定电子电路是否正常工作所需的一个主要部分，辅助部件不需要用于确定电子电路是否正常工作，辅助部件连接到连接到至少一个电路的线路 主要部分，以提供对至少一个主要部分的操作所必需的信号，或者输出通过至少一个主要部分的操作而获得的信号。 这提供了一种电子电路，其能够适当地检测电路布线断开并且容易地检测元件之间的有缺陷的布线，而不需要为电子电路提供用于检测电路布线断开的更多部件。

公开(公告)号：US20110291097A1

公开(公告)日：2011-12-01

申请号：US13138396

申请日：2009-11-05

Applicant: Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

Inventor： Isao Ogasawara ,  Takaharu Yamada ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC: H01L33/16 ,  H01L29/786

CPC classification number: G02F1/136286 ,  G02F1/133345 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  H01L27/1222 ,  H01L27/124

Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.

Abstract translation: 本发明的实施例提供了一种TFT阵列基板，其中TFT元件和与TFT元件相对应的像素电极在矩阵上排列在绝缘基板上，该TFT阵列基板包括：由第一金属材料制成的栅极总线 ; 由第二金属材料制成的源总线; 由第三金属材料制成的像素电极; 由第一金属材料制成的时钟布线; 由第二金属材料制成的分支布线; 以及由第三金属材料制成的连接导体，连接导体在周边区域的连接部分连接时钟布线和分支布线，所述连接部分具有分支布线通孔，该布线通孔使被覆盖的分支布线 与连接导体，并且至少部分地在平面图中与时钟布线重叠。

公开(公告)号：US20110075087A1

公开(公告)日：2011-03-31

申请号：US12994499

申请日：2009-03-27

Applicant: Junichi Morinaga ,  Katsushige Asada ,  Masahiro Yoshida ,  Tetsuya Fujikawa ,  Katsuhiro Mikumo ,  Kuniko Maeno ,  Ryohki Itoh ,  Satoshi Horiuchi ,  Tatsuji Saitoh ,  Isao Ogasawara ,  Kazunori Tanimoto ,  Katsuhiro Okada ,  Toshiaki Fujihara ,  Masakatsu Tominaga

Inventor： Junichi Morinaga ,  Katsushige Asada ,  Masahiro Yoshida ,  Tetsuya Fujikawa ,  Katsuhiro Mikumo ,  Kuniko Maeno ,  Ryohki Itoh ,  Satoshi Horiuchi ,  Tatsuji Saitoh ,  Isao Ogasawara ,  Kazunori Tanimoto ,  Katsuhiro Okada ,  Toshiaki Fujihara ,  Masakatsu Tominaga

IPC: G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/133707 ,  G02F1/134309 ,  G02F1/1393

Abstract: Each of picture elements (14) has a plurality of alignment regions (R1, R2, R3, and R4), in each of which liquid crystal molecules contained in a liquid crystal layer are aligned in a direction that is different from those in the others of the plurality of alignment regions. Each of a plurality of scanning signal lines (32) and a border region (R11 and R12) between corresponding adjacent ones of the plurality of alignment regions (R1, R2, R3, and R4) at least partially overlap each other when viewed from above.

Abstract translation: 每个像素（14）具有多个取向区域（R1，R2，R3和R4），其中液晶层中所含的液晶分子在与其它方向不同的方向上排列 的多个对准区域。 当从上方观察时，多个对准区域（R1，R2，R3和R4）中相应的相邻的对齐区域（R1，R2，R3和R4）之间的多个扫描信号线（32）和边界区域（R11和R12）中的每一个至少部分地彼此重叠 。

公开(公告)号：US20110006780A1

公开(公告)日：2011-01-13

申请号：US12920857

申请日：2009-03-13

Applicant: Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Takehiko Kawamura ,  Hideaki Takizawa

Inventor： Kazunori Tanimoto ,  Isao Ogasawara ,  Masahiro Yoshida ,  Takehiko Kawamura ,  Hideaki Takizawa

IPC: G01R31/04 ,  G09G3/20 ,  G09G3/36

CPC classification number: G01R31/045 ,  G02F1/1345 ,  G02F1/136286 ,  G02F2001/13456 ,  G02F2001/136254

Abstract: Provided is an active matrix substrate having improved display quality without forming an inspection line in a terminal arrangement region for inspecting short circuit between connection lines. Scanning lines (40) include first scanning lines having input ends for a scanning signal on one end side, and second scanning lines having input ends for a scanning signal the other end side. In a display region (4), the first scanning lines and the second scanning lines are formed alternately one by one. An active matrix substrate (2) includes a first inspection line (70) and a second inspection line (72) that cross each of a plurality of first connection lines (61), and a third inspection line (75) and a fourth inspection line (77) that cross each of a plurality of second connection lines (64). The first to the fourth inspection lines (70, 72, 75, 77) are formed in a frame-shaped wiring region (6), excluding the terminal arrangement region (5) and the display region (4).

Abstract translation: 提供一种具有改进的显示质量的有源矩阵基板，而不在端子排列区域中形成检查线，用于检查连接线之间的短路。 扫描线（40）包括在一端侧具有用于扫描信号的输入端的第一扫描线和具有用于扫描信号的另一端侧的输入端的第二扫描线。 在显示区域（4）中，第一扫描线和第二扫描线交替地一个一个地形成。 有源矩阵基板（2）包括跨越多个第一连接线（61）中的每一条的第一检查线（70）和第二检查线（72），以及第三检查线（75）和第四检查线 （77），其跨越多个第二连接线（64）中的每一个。 第一至第四检查线（70,72,75,77）形成在除端子排列区域（5）和显示区域（4）之外的框状布线区域（6）中。

公开(公告)号：US20100283931A1

公开(公告)日：2010-11-11

申请号：US12811343

申请日：2008-12-02

Applicant: Satoshi Horiuchi ,  Takaharu Yamada ,  Isao Ogasawara

Inventor： Satoshi Horiuchi ,  Takaharu Yamada ,  Isao Ogasawara

IPC: H01L33/00 ,  H01L27/06 ,  H01L27/105 ,  G02F1/136

CPC classification number: G02F1/1345 ,  G02F1/1362 ,  G02F1/136286

Abstract: In a TFT array substrate (20), connecting points (P10) of a first metal layer (M1) and a second metal layer (M2) are provided in a peripheral region (A20). A driving circuit (B60b), which is at least a part of a driving circuit (60), is provided between the connecting points (P10) and an edge (24) of the TFT array substrate (20).

Abstract translation: 在TFT阵列基板（20）中，第一金属层（M1）和第二金属层（M2）的连接点（P10）设置在周边区域（A20）中。 作为驱动电路（60）的至少一部分的驱动电路（B60b）设置在TFT阵列基板（20）的连接点（P10）和边缘（24）之间。