公开(公告)号：US20100264507A1

公开(公告)日：2010-10-21

申请号：US12651055

申请日：2009-12-31

申请人： Tetsuo TAKAHASHI ,  Takami Otsuki

发明人： Tetsuo TAKAHASHI ,  Takami Otsuki

IPC分类号： H01L29/06

CPC分类号： H01L29/404 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/7395

摘要： A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

摘要翻译： 半导体器件包括：具有设置在半导体衬底上并与半导体衬底绝缘的具有元件形成区域的主表面，保护环，保护环电极，沟道阻挡区域，沟道阻挡电极和场板的半导体衬底。 场板包括位于半导体衬底的主表面和保护环电极之间的第一部分和位于半导体衬底的主表面和通道阻挡电极之间的第二部分。 当在俯视图中观察时，第一部分具有与保护环电极重叠的部分。 当在平面图中观察时，第二部分具有与通道阻挡电极重叠的部分。 以这种方式，可以获得允许稳定的击穿电压的半导体器件。

公开(公告)号：US20100252904A1

公开(公告)日：2010-10-07

申请号：US12685180

申请日：2010-01-11

申请人： Tetsuo Takahashi ,  Takami Otsuki

发明人： Tetsuo Takahashi ,  Takami Otsuki

IPC分类号： H01L29/06 ,  H01L21/04

CPC分类号： H01L29/063 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

摘要翻译： 半导体包括设置在基板中的N型杂质区。 P型RESURF层设置在N型杂质区的衬底顶面。 P阱的杂质浓度比P型RESURF层高，与N型杂质区的衬底顶面的P型RESURF层接触。 第一高电压侧板与N型杂质区电连接，低压侧板与P型杂质区电连接。 下场板能够产生与衬底的较低的电容耦合。 上场板位于比下场板更远离衬底的位置处，并且能够产生与电容大于低容性耦合的电容的下场板的上电容耦合。

公开(公告)号：US20130082283A1

公开(公告)日：2013-04-04

申请号：US13473991

申请日：2012-05-17

申请人： Takami OTSUKI ,  Taichi OBARA ,  Akira GOTO

发明人： Takami OTSUKI ,  Taichi OBARA ,  Akira GOTO

IPC分类号： H01L29/16 ,  H01L29/02 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/4821 ,  B22D19/00 ,  B22D21/04 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal.

公开(公告)号：US08994141B2

公开(公告)日：2015-03-31

申请号：US12685180

申请日：2010-01-11

申请人： Tetsuo Takahashi ,  Takami Otsuki

发明人： Tetsuo Takahashi ,  Takami Otsuki

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/063 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

摘要翻译： 半导体包括设置在基板中的N型杂质区。 P型RESURF层设置在N型杂质区的衬底顶面。 P阱的杂质浓度比P型RESURF层高，与N型杂质区的衬底顶面的P型RESURF层接触。 第一高电压侧板与N型杂质区电连接，低压侧板与P型杂质区电连接。 下场板能够产生与衬底的较低的电容耦合。 上场板位于比下场板更远离衬底的位置处，并且能够产生与电容大于低容性耦合的电容的下场板的上电容耦合。

公开(公告)号：US09236436B2

公开(公告)日：2016-01-12

申请号：US12651055

申请日：2009-12-31

申请人： Tetsuo Takahashi ,  Takami Otsuki

发明人： Tetsuo Takahashi ,  Takami Otsuki

IPC分类号： H01L23/58 ,  H01L29/40 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/404 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/7395

摘要： A semiconductor device includes: a semiconductor substrate having a main surface having an element formation region, a guard ring, a guard ring electrode, a channel stopper region, a channel stopper electrode, and a field plate disposed over and insulated from the semiconductor substrate. The field plate includes a first portion located between the main surface of the semiconductor substrate and the guard ring electrode, and a second portion located between the main surface of the semiconductor substrate and the channel stopper electrode. The first portion has a portion overlapping with the guard ring electrode when viewed in a plan view. The second portion has a portion overlapping with the channel stopper electrode when viewed in the plan view. In this way, a semiconductor device allowing for stabilized breakdown voltage can be obtained.

摘要翻译： 半导体器件包括：具有设置在半导体衬底上并与半导体衬底绝缘的具有元件形成区域的主表面，保护环，保护环电极，沟道阻挡区域，沟道阻挡电极和场板的半导体衬底。 场板包括位于半导体衬底的主表面和保护环电极之间的第一部分和位于半导体衬底的主表面和通道阻挡电极之间的第二部分。 当在俯视图中观察时，第一部分具有与保护环电极重叠的部分。 当在平面图中观察时，第二部分具有与通道阻挡电极重叠的部分。 以这种方式，可以获得允许稳定的击穿电压的半导体器件。