Methods of fabricating metal hard masks
    1.
    发明授权
    Methods of fabricating metal hard masks 有权
    制造金属硬掩模的方法

    公开(公告)号:US08623468B2

    公开(公告)日:2014-01-07

    申请号:US13343857

    申请日:2012-01-05

    Abstract: Methods of fabricating a metal hard mask and a metal hard mask fabricated by such methods are described. The method includes flowing at least one metal reactant gas into a reaction chamber configured to perform chemical vapor deposition (CVD), wherein the at least one metal reactant gas includes a metal-halogen gas or a metal-organic gas. The method further includes depositing a hard mask metal layer by CVD using the at least one metal reactant gas.

    Abstract translation: 描述了通过这种方法制造金属硬掩模和金属硬掩模的方法。 该方法包括将至少一种金属反应物气体流入配置成执行化学气相沉积(CVD)的反应室,其中至少一种金属反应物气体包括金属卤素气体或金属有机气体。 该方法还包括使用至少一种金属反应物气体通过CVD沉积硬掩模金属层。

    METAL HARD MASK FABRICATION
    2.
    发明申请
    METAL HARD MASK FABRICATION 有权
    金属硬掩模制造

    公开(公告)号:US20130174982A1

    公开(公告)日:2013-07-11

    申请号:US13343857

    申请日:2012-01-05

    Abstract: The present disclosure provides for methods of fabricating a metal hard mask and a metal hard mask fabricated by such methods. A method includes flowing at least one metal reactant gas into a reaction chamber configured to perform chemical vapor deposition (CVD), wherein the at least one metal reactant gas includes a metal-halogen gas or a metal-organic gas. The method further includes depositing a hard mask metal layer by CVD using the at least one metal reactant gas.

    Abstract translation: 本公开提供了通过这种方法制造的金属硬掩模和金属硬掩模的制造方法。 一种方法包括将至少一种金属反应物气体流入被配置为进行化学气相沉积(CVD)的反应室,其中所述至少一种金属反应物气体包括金属卤素气体或金属有机气体。 该方法还包括使用至少一种金属反应物气体通过CVD沉积硬掩模金属层。

    Integration of bottom-up metal film deposition
    4.
    发明授权
    Integration of bottom-up metal film deposition 有权
    整合自下而上的金属膜沉积

    公开(公告)号:US08088685B2

    公开(公告)日:2012-01-03

    申请号:US12702525

    申请日:2010-02-09

    Abstract: The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios.

    Abstract translation: 自下而上金属沉积以填充互连和替代栅极结构的方法的所述实施例使得能够在没有空隙的情况下间隙填充具有高纵横比的精细特征,并提供具有良好膜质量的金属膜。 通过气体簇离子束(GCIB)沉积的金属膜的原位预处理允许去除表面杂质和表面氧化物以改善下层与沉积的金属膜之间的粘附。 通过使用高能量的低频光源在较低温度下通过光致化学气相沉积(PI-CVD)沉积的金属膜表现出液体性质,这允许金属膜从下向上填充精细特征。 通过PI-CVD沉积的金属膜的后沉积退火致密化金属膜并从金属膜去除残留的气态物质。 对于先进的制造,这种自下而上的金属沉积方法解决了具有高纵横比的精细特征的间隙填充的挑战。

    Methods of Forming Tungsten Contacts by Chemical Vapor Deposition
    6.
    发明申请
    Methods of Forming Tungsten Contacts by Chemical Vapor Deposition 有权
    通过化学气相沉积形成钨触点的方法

    公开(公告)号:US20060115985A1

    公开(公告)日:2006-06-01

    申请号:US10904817

    申请日:2004-11-30

    Applicant: Su-Horng Lin

    Inventor: Su-Horng Lin

    CPC classification number: H01L21/76843 H01L21/76876 H01L21/76877

    Abstract: Described are methods of manufacturing a semiconductor device with tungsten contacts between two conductive layers on different interconnect levels. A barrier adhesion layer is formed over interconnect openings followed by a tungsten nucleation film being deposited at a nucleation temperature and a tungsten bulk deposition film being deposited at a bulk deposition temperature, wherein the nucleation temperature is higher than the bulk deposition temperature such that the difference between the nucleation temperature and the bulk deposition temperature improves tungsten gap-fill capability.

    Abstract translation: 描述了制造具有不同互连层上的两个导电层之间的钨触点的半导体器件的方法。 在互连开口之后形成阻挡粘附层,随后在成核温度下沉积钨成核膜,并以体积沉积温度沉积钨体沉积膜,其中成核温度高于体积沉积温度,使得差异 在成核温度和体积沉积温度之间提高钨间隙填充能力。

    METHOD OF FORMING A SINGLE METAL THAT PERFORMS N AND P WORK FUNCTIONS IN HIGH-K/METAL GATE DEVICES
    7.
    发明申请
    METHOD OF FORMING A SINGLE METAL THAT PERFORMS N AND P WORK FUNCTIONS IN HIGH-K/METAL GATE DEVICES 有权
    形成高K /金属门装置中的N和P功能的单金属的方法

    公开(公告)号:US20140319619A1

    公开(公告)日:2014-10-30

    申请号:US14329452

    申请日:2014-07-11

    Applicant: Su-Horng Lin

    Inventor: Su-Horng Lin

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底,在半导体衬底上形成高k电介质层,在高k电介质层上形成金属层,金属层具有第一功函数,保护 在第一区域中的金属层,用包含碳和氮的去耦合等离子体处理第二区域中的金属层,以及在第一区域中形成第一栅极结构,在第二区域中形成第二栅极结构。 第一栅极结构包括高k电介质层和未处理的金属层。 第二栅极结构包括高k电介质层和经处理的金属层。

    Method of forming a single metal that performs N and P work functions in high-K/metal gate devices
    8.
    发明授权
    Method of forming a single metal that performs N and P work functions in high-K/metal gate devices 有权
    在高K /金属栅极器件中形成执行N和P功能的单个金属的方法

    公开(公告)号:US08778754B2

    公开(公告)日:2014-07-15

    申请号:US12364289

    申请日:2009-02-02

    Applicant: Su-Horng Lin

    Inventor: Su-Horng Lin

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底,在半导体衬底上形成高k电介质层,在高k电介质层上形成金属层,金属层具有第一功函数,保护 在第一区域中的金属层,用包含碳和氮的去耦合等离子体处理第二区域中的金属层,以及在第一区域中形成第一栅极结构,在第二区域中形成第二栅极结构。 第一栅极结构包括高k电介质层和未处理的金属层。 第二栅极结构包括高k电介质层和经处理的金属层。

    Method of fabricating high-k metal gate devices
    10.
    发明授权
    Method of fabricating high-k metal gate devices 有权
    制造高k金属栅极器件的方法

    公开(公告)号:US07776757B2

    公开(公告)日:2010-08-17

    申请号:US12354394

    申请日:2009-01-15

    Abstract: The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F-] concentration greater than 0.01M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts.

    Abstract translation: 本公开提供了一种用于制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底,在半导体衬底上形成高k电介质层,通过原位沉积工艺形成第一金属层和第一硅层,图案化第一硅 以去除覆盖在第二区域上的部分,使用图案化的第一硅层作为掩模来图案化第一金属层,以及去除图案化的第一硅层,包括施加溶液。 该溶液包括具有大于0.01M的[F-]浓度的第一组分,构成为将溶液的pH调节至约4.3至约6.7的第二组分,以及构成为将溶液的电位调节为 大于-1.4伏。

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