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    Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes
    2.
    发明授权
    Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权
    半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元

    公开(公告)号：US08482083B2

    公开(公告)日：2013-07-09

    申请号：US12821329

    申请日：2010-06-23

    Applicant: Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L29/76 ,  H01L27/11

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

    Abstract translation: 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低 导致出现微图案化困难的问题。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20130049131A1

    公开(公告)日：2013-02-28

    申请号：US13616435

    申请日：2012-09-14

    Applicant: Kenichi OSADA ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    Inventor： Kenichi OSADA ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L27/092

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.

    Abstract translation: 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区域的衬底电接触，这将导致不对称性的降低 导致微图案化困难。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

    Semiconductor integrated circuit device and process for manufacturing the same
    4.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US07834420B2

    公开(公告)日：2010-11-16

    申请号：US12335302

    申请日：2008-12-15

    Applicant: Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    Inventor： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    IPC: H01L29/00 ,  H01L21/8234

    CPC classification number: H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

    Abstract translation: 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。 此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。 此外，通过使用诸如硅化的电阻降低装置来形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07781846B2

    公开(公告)日：2010-08-24

    申请号：US12348524

    申请日：2009-01-05

    Applicant: Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC: H01L29/76 ,  H01L27/11

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

    Abstract translation: 现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致 不对称性导致了微图案化困难的问题的发生。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07608899B2

    公开(公告)日：2009-10-27

    申请号：US11936443

    申请日：2007-11-07

    Applicant: Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    Inventor： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    IPC: H01L29/76 ,  H01L29/94

    CPC classification number: H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

    Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate lectrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

    Abstract translation: 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅极电介质膜6,7和栅极放电层8,9作为MOS晶体管。 氧化锆或氧化铪被用作栅极电介质膜6,7的主要成分。例如通过CVD形成栅极绝缘膜6,7。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。在使用其表面为（111）的基板的情况下， 在使用表面为（001）晶面的硅衬底的情况下，氧的扩散系数小于氧的扩散系数的1/100，并且控制氧扩散。 因此，控制氧扩散，防止漏电流的产生，提高性能。 实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

    Method of manufacturing a semiconductor integrated circuit device
    7.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device 有权
    半导体集成电路器件的制造方法

    公开(公告)号：US07488639B2

    公开(公告)日：2009-02-10

    申请号：US11342695

    申请日：2006-01-31

    Applicant: Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

    Inventor： Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda

    IPC: H01L21/8238

    CPC classification number: H01L27/11 ,  H01L27/1104

    Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

    Abstract translation: 为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面 其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。 在布线上形成用作电容绝缘膜的氮化硅膜和上电极。 电容可以由布线，氮化硅膜和上电极形成。

    Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring
    10.
    发明授权
    Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring 有权
    具有（111）取向的衬底上的场效应晶体管具有氧化锆栅极绝缘体和钴或镍硅化物布线

    公开(公告)号：US07358578B2

    公开(公告)日：2008-04-15

    申请号：US10155833

    申请日：2002-05-22

    Applicant: Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    Inventor： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideo Miura ,  Shuji Ikeda

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00

    CPC classification number: H01L21/823462 ,  H01L21/28097 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/823412 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78696

    Abstract: Diffusion layers 2-5 are formed on a silicon substrate 1, and gate dielectric films 6, 7 and gate electrodes 8, 9 are formed on these diffusion layers 2-5 so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films 6, 7. Gate dielectric films 6, 7 are formed, for example, by CVD. As substrate 1, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrate 1 or gate electrodes 8, 9. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

    Abstract translation: 在硅衬底1上形成扩散层2-5，并且在这些扩散层2-5上形成栅电介质膜6,7和栅电极8，以便成为MOS晶体管。 氧化锆或氧化铪被用作栅介质膜6,7的主要成分。 栅介质膜6,7例如通过CVD形成。 作为基板1，使用表面为（111）晶面的其中之一，以防止氧扩散到硅基板1或栅电极8,9中。 在使用表面为（111）晶面的基板的情况下，在使用表面为（001）晶面的硅基板的情况下，氧的扩散系数小于1/100，氧气 扩散被控制。 因此，控制氧扩散，防止漏电流的产生，提高性能。 实现了具有高可靠性并且能够防止伴随小型化的特性劣化的半导体器件。

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