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    Short arc type discharge lamp
    1.
    发明授权
    Short arc type discharge lamp 有权
    短弧型放电灯

    公开(公告)号：US08400060B2

    公开(公告)日：2013-03-19

    申请号：US13245028

    申请日：2011-09-26

    Applicant: Tomoyoshi Arimoto ,  Mitsuru Ikeuchi ,  Akihiro Shimizu

    Inventor： Tomoyoshi Arimoto ,  Mitsuru Ikeuchi ,  Akihiro Shimizu

    IPC: H01J17/04

    CPC classification number: H01J61/0735 ,  H01J61/0732 ,  H01J61/86

    Abstract: A short arc type discharge lamp wherein a cathode and an anode are arranged opposite to each other in an interior of a light emitting tube and said cathode consists of a main body part with tungsten as the main constituent and an emitter part comprised of thoriated tungsten, wherein an oxygen content of the main body part of said cathode is lower than that of the emitter part, and band-shaped tungsten carbide is formed at the tip end face of the emitter part of said cathode.

    Abstract translation: 一种短弧型放电灯，其中阴极和阳极在发光管的内部彼此相对布置，并且所述阴极由以钨为主要成分的主体部分和由钍钨组成的发射极部分组成， 其中所述阴极的主体部分的氧含量低于发射极部分的氧含量，并且在所述阴极的发射极部分的末端面上形成带状碳化钨。

    SHORT ARC TYPE DISCHARGE LAMP
    2.
    发明申请
    SHORT ARC TYPE DISCHARGE LAMP 有权
    短弧型放电灯

    公开(公告)号：US20120181925A1

    公开(公告)日：2012-07-19

    申请号：US13348301

    申请日：2012-01-11

    Applicant: Tomoyoshi Arimoto ,  Akihiro Shimizu ,  Mitsuru Ikeuchi

    Inventor： Tomoyoshi Arimoto ,  Akihiro Shimizu ,  Mitsuru Ikeuchi

    IPC: H01J61/04

    CPC classification number: H01J61/0732 ,  H01J61/0735 ,  H01J61/86

    Abstract: A short arc type discharge lamp includes a cathode and an anode arranged inside an arc tube to face each other. The cathode comprises a main body portion made of tungsten and an emitter portion made of thoriated tungsten that is joined at the tip of the main body portion, where a metal oxide other than thorium (Th) is contained in the main body portion of the cathode, and a tungsten carbide layer is formed on the metal oxide.

    Abstract translation: 短弧型放电灯包括阴极和布置在电弧管内的阳极以彼此面对。 阴极包括由钨制成的主体部分和由钍钨制成的发射极部分，其连接在主体部分的尖端处，其中除了钍（Th）之外的金属氧化物被包含在阴极的主体部分中 并且在金属氧化物上形成碳化钨层。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US20090140349A1

    公开(公告)日：2009-06-04

    申请号：US12335302

    申请日：2008-12-15

    Applicant: Shuji IKEDA ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    Inventor： Shuji IKEDA ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    IPC: H01L27/092

    CPC classification number: H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

    Abstract translation: 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。 此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。 此外，通过使用诸如硅化的电阻降低装置来形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

    Semiconductor integrated circuit device and process for manufacturing the same
    9.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US07511377B2

    公开(公告)日：2009-03-31

    申请号：US11834095

    申请日：2007-08-06

    Applicant: Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    Inventor： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

    IPC: H01L23/52 ,  H01L29/00

    CPC classification number: H01L27/11 ,  G11C11/412 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  Y10S257/904

    Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

    Abstract translation: 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容元件。 此外，通过在第一导电层上叠加局部布线，在局部布线和第一导电层之间形成电容元件。 此外，通过使用诸如硅化的电阻降低装置来形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的装置的手段。

    Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance
    10.
    发明授权
    Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance 失效
    将局部应力施加到PFET和NFET晶体管的通道以提高性能的结构和方法

    公开(公告)号：US07414293B2

    公开(公告)日：2008-08-19

    申请号：US11541575

    申请日：2006-10-03

    Applicant: Akihiro Shimizu ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

    Inventor： Akihiro Shimizu ,  Nagatoshi Ooki ,  Yusuke Nonaka ,  Katsuhiko Ichinose

    IPC: H01L27/092

    CPC classification number: H01L29/7845 ,  H01L21/0217 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device has an n channel conductivity type field effect transistor having a channel formation region formed in a first region on one main surface of a semiconductor substrate and a p channel conductivity type field effect transistor having a channel formation region formed in a second region on the main surface of the semiconductor substrate, which second region is different from the first region. An internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is different from an internal stress generated in the channel formation region of the p channel conductivity type field effect transistor. The internal stress generated in the channel formation region of the n channel conductivity type field effect transistor is a tensile stress, while the internal stress generated in the channel formation region of the p channel conductivity type field effect transistor is a compressive stress.

    Abstract translation: 半导体器件具有n沟道导电型场效应晶体管，其具有形成在半导体衬底的一个主表面上的第一区域中的沟道形成区域和具有形成在第二区域中的沟道形成区域的ap沟道导电型场效应晶体管， 半导体衬底的主表面，该第二区域与第一区域不同。 在n沟道导电型场效应晶体管的沟道形成区域中产生的内应力与在p沟道导电型场效应晶体管的沟道形成区域中产生的内应力不同。 在n沟道导电型场效应晶体管的沟道形成区域中产生的内应力是拉伸应力，而在p沟道导电型场效应晶体管的沟道形成区域中产生的内应力是压应力。

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