Invention Grant
- Patent Title: Semiconductor integrated circuit device and process for manufacturing the same
- Patent Title (中): 半导体集成电路器件及其制造方法
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Application No.: US11834095Application Date: 2007-08-06
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Publication No.: US07511377B2Publication Date: 2009-03-31
- Inventor: Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
- Applicant: Shuji Ikeda , Toshiaki Yamanaka , Kenichi Kikushima , Shinichiro Mitani , Kazushige Sato , Akira Fukami , Masaya Iida , Akihiro Shimizu
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP6-114925 19940527; JP6-153163 19940705
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L29/00

Abstract:
A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.
Public/Granted literature
- US20080099854A1 Semiconductor integrated circuit device and process for manufacturing the same Public/Granted day:2008-05-01
Information query
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