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    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5412615A

    公开(公告)日：1995-05-02

    申请号：US166099

    申请日：1993-12-14

    申请人： Hiromi Noro ,  Shinnosuke Kamata ,  Yoshinori Okajima

    发明人： Hiromi Noro ,  Shinnosuke Kamata ,  Yoshinori Okajima

    IPC分类号： G06F9/38 ,  G11C7/22 ,  G11C11/407 ,  G11C11/413 ,  G11C11/417 ,  G11C8/00

    CPC分类号： G11C7/225 ,  G11C7/22

    摘要： This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.

    摘要翻译： 本发明提供一种其中消除了永恒时钟信号和内部时钟信号之间的时间差的装置，并且其中即使在高操作频率下也实现高运行速度而不引起错误的电路操作。 半导体集成电路器件配备有信号发生器，用于产生用于从外部时钟信号确定内部电路的操作定时的内部时钟信号。 半导体集成电路器件包括延迟单元，用于通过将信号发生器的输出延迟通过减去与电路延迟相对应的时间而获得的时间，使得外部时钟信号的边沿与内部时钟信号的边缘一致 信号发生器从对应于外部时钟信号的1/2周期的一些整数倍的时间开始。

    Memory device, memory controller and memory system
    8.
    发明申请
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：US20080151677A1

    公开(公告)日：2008-06-26

    申请号：US11698286

    申请日：2007-01-26

    申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    IPC分类号： G11C8/12

    CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

    摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

    摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。

    Multiple chip package and IC chips
    10.
    发明申请
    Multiple chip package and IC chips 有权
    多芯片封装和IC芯片

    公开(公告)号：US20060092752A1

    公开(公告)日：2006-05-04

    申请号：US11043993

    申请日：2005-01-28

    申请人： Fusao Seki ,  Tatsushi Otsuka ,  Masanori Kurita ,  Shinnosuke Kamata ,  Toshiya Uchida ,  Hiroyoshi Tomita ,  Hiroyuki Kobayashi

    发明人： Fusao Seki ,  Tatsushi Otsuka ,  Masanori Kurita ,  Shinnosuke Kamata ,  Toshiya Uchida ,  Hiroyoshi Tomita ,  Hiroyuki Kobayashi

    IPC分类号： G11C8/00

    CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L2224/49113 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.

    摘要翻译： 时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。 时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。 时钟接收板电连接到时钟输出板和返回时钟接收板。 多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。