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公开(公告)号：US08547776B2
公开(公告)日：2013-10-01
申请号：US13031080
申请日：2011-02-18
申请人： Takaaki Suzuki , Shinnosuke Kamata
发明人： Takaaki Suzuki , Shinnosuke Kamata
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
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公开(公告)号：US20130201751A1
公开(公告)日：2013-08-08
申请号：US13601406
申请日：2012-08-31
申请人： Takaaki Suzuki , Shinnosuke Kamata
发明人： Takaaki Suzuki , Shinnosuke Kamata
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
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公开(公告)号：US20060294322A1
公开(公告)日：2006-12-28
申请号：US11512319
申请日：2006-08-30
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F13/28
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
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公开(公告)号：US08717842B2
公开(公告)日：2014-05-06
申请号：US13601406
申请日：2012-08-31
申请人： Takaaki Suzuki , Shinnosuke Kamata
发明人： Takaaki Suzuki , Shinnosuke Kamata
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
摘要翻译： 半导体存储器件包括多个N个外部端口，每个N个外部端口接收命令;以及内部电路，其在输入到一个外部端口的命令的最小间隔期间执行至少N次访问操作。
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公开(公告)号：US07120761B2
公开(公告)日：2006-10-10
申请号：US10284092
申请日：2002-10-31
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G06F12/00
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
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公开(公告)号：US07911825B2
公开(公告)日：2011-03-22
申请号：US11512319
申请日：2006-08-30
申请人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
发明人： Yasurou Matsuzaki , Takaaki Suzuki , Masafumi Yamazaki , Kenichi Kawasaki , Shinnosuke Kamata , Ayako Sato , Masato Matsumiya
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G06F13/1605 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/24 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/409 , G11C11/4093 , G11C2207/107 , G11C2207/108
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
摘要翻译： 半导体存储器件包括多个N个外部端口，每个N个外部端口接收命令;以及内部电路，其在输入到一个外部端口的命令的最小间隔期间执行至少N次访问操作。
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公开(公告)号：US20100146201A1
公开(公告)日：2010-06-10
申请号：US12612215
申请日：2009-11-04
申请人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Tomohiro Kawakubo , Syusaku Yamaguchi , Hitoshi Ikeda , Toshiya Uchida , Hiroyuki Kobayashi , Tatsuya Kanda , Yoshinobu Yamamoto , Satoru Shirakawa , Tetsuo Miyamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C7/1027 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.
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公开(公告)号：US20080181027A1
公开(公告)日：2008-07-31
申请号：US12000952
申请日：2007-12-19
申请人： Takahiro Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
发明人： Takahiro Sato , Toshiya Uchida , Tatsuya Kanda , Tetsuo Miyamoto , Satoru Shirakawa , Yoshinobu Yamamoto , Tatsushi Otsuka , Hidenaga Takahashi , Masanori Kurita , Shinnosuke Kamata , Ayako Sato
CPC分类号： G11C11/4087 , G09G5/393 , G09G5/395 , G11C8/12
摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.
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公开(公告)号：US07323789B2
公开(公告)日：2008-01-29
申请号：US11043993
申请日：2005-01-28
申请人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
发明人： Fusao Seki , Tatsushi Otsuka , Masanori Kurita , Shinnosuke Kamata , Toshiya Uchida , Hiroyoshi Tomita , Hiroyuki Kobayashi
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/49113 , H01L2924/3011 , H01L2924/00
摘要： A clock output pad and a return clock receiving pad are disposed on a logic chip at a portion near a side of an integrated circuit chip and a portion near another side of the integrated circuit chip that opposes to the side. A clock receiving pad is disposed on a memory chip at portion near the side and the other side respectively. The clock receiving pad is electrically connected to the clock output pad and the return clock receiving pad. A plurality of clock signals are supplied from the logic chip to the memory chip, and a plurality of return clock signals are returned from the memory chip to the logic chip.
摘要翻译： 时钟输出板和返回时钟接收焊盘设置在集成电路芯片的靠近侧面的部分和与集成电路芯片的与侧面相反的另一侧的部分的逻辑芯片上。 时钟接收垫分别在靠近侧面和另一侧的部分设置在存储器芯片上。 时钟接收板电连接到时钟输出板和返回时钟接收板。 多个时钟信号从逻辑芯片提供给存储器芯片，并且多个返回时钟信号从存储器芯片返回到逻辑芯片。
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公开(公告)号：US6063640A
公开(公告)日：2000-05-16
申请号：US30349
申请日：1998-02-25
申请人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
发明人： Masataka Mizukoshi , Hidehiko Akasaki , Masao Nakano , Yasuhiro Fujii , Shinnosuke Kamata , Makoto Yanagisawa , Yasurou Matsuzaki , Toyonobu Yamada , Masami Matsuoka , Hiroyoshi Tomita
CPC分类号： H01L22/32 , H01L22/22 , H01L2224/05554 , Y10S438/977
摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.
摘要翻译： 半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤 来自半导体晶片表面的临时测试膜。 临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。 所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。
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