公开(公告)号：US5352935A

公开(公告)日：1994-10-04

申请号：US955287

申请日：1992-10-01

申请人： Ryuji Yamamura ,  Tadahiko Sugibayashi ,  Takahiro Hara

发明人： Ryuji Yamamura ,  Tadahiko Sugibayashi ,  Takahiro Hara

IPC分类号： G11C11/413 ,  G05F1/46 ,  G05F1/56 ,  G05F3/24 ,  G11C11/407 ,  H03K17/24

CPC分类号： G05F1/465

摘要： A semiconductor integrated circuit device has a first internal voltage controlling circuit which lowers an external power source voltage and produces a predetermined internal power source voltage. The device further has a second internal voltage controlling circuit formed by an internal-voltage drop detection circuit for detecting the lowering of the internal power source voltage from a predetermined reference voltage and a switching circuit for causing the external power source voltage to be directly connected to an internal voltage output terminal based on an output from the internal-voltage drop detection circuit. The internal power source voltage is maintained close to the required value thereby preventing a deterioration of circuit performance even when the external power source voltage drops close to the internal power source voltage.

摘要翻译： 半导体集成电路器件具有第一内部电压控制电路，其降低外部电源电压并产生预定的内部电源电压。 该装置还具有由内部电压降检测电路形成的第二内部电压控制电路，用于检测来自预定参考电压的内部电源电压的降低以及用于使外部电源电压直接连接到 基于来自内部电压降检测电路的输出的内部电压输出端子。 内部电源电压保持接近所需值，从而即使当外部电源电压下降到接近内部电源电压时也防止电路性能的劣化。

公开(公告)号：US5272677A

公开(公告)日：1993-12-21

申请号：US958795

申请日：1992-10-09

申请人： Ryuji Yamamura

发明人： Ryuji Yamamura

IPC分类号： G11C11/419 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C11/4091

摘要： A dynamic random access memory device includes a plurality of memory cell plates each having memory cells and a sense amplifier circuit array selectively coupled with the memory cells, and the sense amplifier circuit array selectively enters a standby mode and amplifying mode depending upon first and second driving signals supplied thereto, wherein the first and second driving signals are regulated to an intermediate voltage level between a step-down power voltage level and a ground voltage level in the standby mode with a main step-down power voltage signal supplied from a main step-down circuit; however, the first and second driving signals are changed to the step-down voltage level and the ground voltage level with an auxiliary step-down power voltage signal produced from an external power voltage signal at an auxiliary step-down circuit exclusively associated therewith so that undesirable voltage fluctuation hardly takes place on a main step-down power voltage line.

摘要翻译： 动态随机存取存储器件包括多个存储单元板，每个存储单元板具有存储单元和与存储单元选择性耦合的读出放大器电路阵列，并且读出放大器电路阵列根据第一和第二驱动选择性地进入待机模式和放大模式 提供给其的信号，其中第一和第二驱动信号通过从主步进电源提供的主降压电源电压信号在待机模式下被调节到降压功率电压电平和接地电压电平之间的中间电压电平， 下电路 然而，第一和第二驱动信号由辅助降压电路产生的辅助降压功率电压信号改变为降压电压和接地电压电平，该辅助降压电压信号在与其完全相关的辅助降压电路处产生，使得 在主降压电源线上几乎不发生不期望的电压波动。

公开(公告)号：US5027252A

公开(公告)日：1991-06-25

申请号：US596452

申请日：1990-10-12

申请人： Ryuji Yamamura

发明人： Ryuji Yamamura

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/08 ,  H01L29/78

CPC分类号： H01L27/0266

摘要： A semiconductor input protection device is disclosed which comprises a well type punch-through transistor consisting of a pair of parallel-opposed well layers through intermediation of a field oxide film, one of which is connected to an input terminal and the other to a reference potential. The device further comprises an impurity diffusion layer resistance with an end thereof connected to the input terminal. The lower limit distance between the opposed sides of the well layers to each other and the channel stopper is set to be smaller than that between the channel stopper and the input terminal-side well layer in the area where the latter and the impurity diffusion layer resistance intersect. The two lower limit distances depend on punch-through voltage, the width of the depletion layer in the well layer at applied punch-through voltage, and the junction disruptive strength of the well layer.

公开(公告)号：US5289061A

公开(公告)日：1994-02-22

申请号：US937055

申请日：1992-08-26

申请人： Tadahiko Sugibayashi ,  Yasuji Koshikawa ,  Ryuji Yamamura

发明人： Tadahiko Sugibayashi ,  Yasuji Koshikawa ,  Ryuji Yamamura

IPC分类号： H03K19/0948 ,  G11C11/407 ,  G11C11/409 ,  H03K19/0185 ,  H03K5/00

CPC分类号： H03K19/018521

摘要： An output gate according to the present invention includes a CMOS gate composed of a P-MOS transistor connected at a source to an external power supply and a first N-MOS transistor connected at a source to ground, and a second N-MOS transistor connected between ground and the first N-MOS transistor by a source-drain path. The second N-MOS transistor is connected at a gate to an external power supply.

摘要翻译： 根据本发明的输出门包括由源极连接到外部电源的P-MOS晶体管和连接到源极的第一N-MOS晶体管构成的CMOS栅极和连接到第二N-MOS晶体管的第二N-MOS晶体管 通过源极 - 漏极路径在地和第一N-MOS晶体管之间。 第二N-MOS晶体管在栅极连接到外部电源。

公开(公告)号：US4828695A

公开(公告)日：1989-05-09

申请号：US154581

申请日：1988-02-10

申请人： Ryuji Yamamura ,  Mikio Tsuboi ,  Keishi Kitagawa ,  Masaru Abe

发明人： Ryuji Yamamura ,  Mikio Tsuboi ,  Keishi Kitagawa ,  Masaru Abe

IPC分类号： B01J20/286 ,  B01D15/08 ,  B01J20/281 ,  B01J20/32 ,  G01N30/88

CPC分类号： B01D15/08 ,  B01J20/28004 ,  B01J20/28057 ,  B01J20/28078 ,  B01J20/286 ,  B01J20/3092 ,  B01J20/3204 ,  B01J20/3257 ,  B01J20/3263 ,  B01J20/327 ,  B01J2220/54 ,  B01J2220/58 ,  Y10T428/2991 ,  Y10T428/2996 ,  Y10T428/2998

摘要： A novel packing material suitable for high pressure liquid chromatography comprising the chemically bonded, crosslinked reaction product of porous inorganic particles, with an organic silane compound having epoxy groups on the surface of the particles, and then with polyvinyl alcohol, in which the hydroxyl groups of the polyvinyl alcohol and the epoxy groups on the silane moieties react to form ether bonds, which cover almost or almost completely the residual silica hydroxyl groups on the surface of the support.

摘要翻译： 一种适用于高压液相色谱的新型包装材料，其包括多孔无机颗粒的化学键合的交联反应产物，在颗粒表面上具有环氧基的有机硅烷化合物，然后与聚乙烯醇反应，其中羟基 硅烷部分上的聚乙烯醇和环氧基团反应形成醚键，其几乎或几乎完全覆盖载体表面上残留的二氧化硅羟基。

公开(公告)号：US5831999A

公开(公告)日：1998-11-03

申请号：US814573

申请日：1997-03-10

申请人： Ryuji Yamamura

发明人： Ryuji Yamamura

IPC分类号： G11B20/18 ,  H03M13/00 ,  H03M13/15 ,  H04L1/00 ,  H03M13/22

CPC分类号： H03M13/151 ,  G11B20/1813

摘要： Disclosed is method of correcting code errors included in digital data that are structured in unit of frames, using first and second series of parity data. The method includes computing a first group of syndromes for the digital data using the first series of parity data. Then, a number of code errors included in the digital data is primarily decided based on the first group of syndromes, and the number of code errors included in the digital data is monitored in a frame by frame manner. In addition, the method includes primarily correcting at least one code error using the first group of syndromes and affixing an error flag to the digital data based on a result of monitoring the number of code errors. Then, a second group of syndromes for the digital data is generated using the second series of parity data. The method further includes secondarily deciding a number of code errors included in the digital data based on the second group of syndromes and the error flag, and further secondarily correcting at least one code error using the second group of syndromes.

摘要翻译： 公开了使用第一和第二系列奇偶校验数据校正以帧为单位构成的数字数据中包含的码错误的方法。 该方法包括使用第一系列奇偶校验数据来计算用于数字数据的第一组综合征。 然后，主要基于第一组校正子来确定数字数据中包含的多个代码错误，并且逐帧地监视包含在数字数据中的代码错误的数量。 此外，该方法包括基于监视代码错误数量的结果，主要使用第一组综合征校正至少一个代码错误，并将错误标志附加到数字数据。 然后，使用第二系列奇偶校验数据生成用于数字数据的第二组综合征。 该方法还包括基于第二组综合征和错误标志来二次确定包括在数字数据中的代码错误的数量，并且进一步使用第二组校正子来校正至少一个代码错误。

公开(公告)号：US5250983A

公开(公告)日：1993-10-05

申请号：US911475

申请日：1992-07-10

申请人： Ryuji Yamamura

发明人： Ryuji Yamamura

IPC分类号： G03F1/42 ,  G03F1/70 ,  G03F7/20 ,  G03F9/00 ,  H01J37/304 ,  H01L21/027 ,  G03B27/28

CPC分类号： G03F9/7084 ,  G03F7/70425 ,  G03F9/7076 ,  H01J37/3045 ,  H01J2237/31767

摘要： An original layout pattern for reticle includes a tip pattern region, a scribe region formed around the tip pattern region, and alignment marks formed in the scribe region. Each end of the alignment marks is not reached to a edge of the original layout pattern. Therefore, when the original layout pattern is formed on the reticle side by side in predetermined times, the alignment marks positioned at an inner portion between two adjacent patterns are separated from each other.

摘要翻译： 用于掩模版的原始布局图案包括尖端图案区域，形成在尖端图案区域周围的划线区域，以及形成在划线区域中的对准标记。 对准标记的每一端都没有到达原始布局图案的边缘。 因此，当在规定时间内并行地在掩模版上形成原始布局图案时，位于两个相邻图案之间的内部的对准标记彼此分离。