公开(公告)号：US06759717B2

公开(公告)日：2004-07-06

申请号：US09800039

申请日：2001-03-06

申请人： Pervez Hassan Sagarwala ,  Mehdi Zamanian ,  Ravi Sundaresan

发明人： Pervez Hassan Sagarwala ,  Mehdi Zamanian ,  Ravi Sundaresan

IPC分类号： H01L2976

CPC分类号： H01L21/823814 ,  Y10S257/90

摘要： A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device. The resulting integrated circuit has an LDD n-channel transistor and a p-channel transistor without an LDD region.

摘要翻译： 提供一种制造具有n沟道和p沟道晶体管的集成电路的方法。 该方法包括形成用于与栅电极自对准的n沟道晶体管的LDD区域。 然后在结构上形成第一氧化物，并且n型硅区域通过第一氧化物与p +型掺杂剂注入，以形成p沟道晶体管的源极和漏极区域。 在结构上形成第二氧化物。 然后蚀刻两个氧化物层以提供侧壁间隔物，其具有由第一氧化物形成的内部部分和由第二氧化物形成的外部部分。 p型硅区域注入n +型掺杂剂以形成n沟道晶体管的低电阻率区域。 在器件的进一步热处理期间，p沟道晶体管的源极和漏极中的p +注入通常在向栅极方向扩散。 所得到的集成电路具有LDD n沟道晶体管和没有LDD区的p沟道晶体管。

公开(公告)号：US06544824B1

公开(公告)日：2003-04-08

申请号：US10038390

申请日：2002-01-03

申请人： Yelehanka Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung

发明人： Yelehanka Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung

IPC分类号： H01L2100

CPC分类号： H01L29/66666

摘要： A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.

摘要翻译： 一种垂直晶体管的制造方法。 在衬底中形成掺杂区域。 我们在衬底上依次形成：第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层。 通过第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层形成沟槽。 沟槽有侧壁。 栅极电介质层形成在沟槽的侧壁上。 我们在沟槽中依次形成：第一掺杂层，第一沟道层，第二掺杂层，第三掺杂层，第二沟道层和第四掺杂层。 在该结构上形成盖层。 触点优选地形成于掺杂区域，掺杂层和栅电极。

公开(公告)号：US06468877B1

公开(公告)日：2002-10-22

申请号：US09907651

申请日：2001-07-19

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

IPC分类号： H01L2176

CPC分类号： H01L21/7682 ,  H01L21/764 ,  H01L21/823468 ,  H01L29/4983

摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.

摘要翻译： 一种制造半导体器件的气隙间隔物的方法，包括以下步骤。 提供具有至少一对限定有源区域的STI的半导体衬底。 在有源区内的基板上形成栅电极。 栅电极具有底层栅介电层。 在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。 在衬垫氧化物层上形成衬里氮化物层。 在结构上形成厚的氧化物层。 厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。 用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。 在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。 蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。 栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

公开(公告)号：US06455377B1

公开(公告)日：2002-09-24

申请号：US09765040

申请日：2001-01-19

申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/1054 ,  H01L29/66916 ,  H01L29/7827 ,  H01L29/802

摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.

摘要翻译： 一种制造垂直沟道晶体管的方法，包括以下步骤。 提供具有上表面的半导体衬底。 在半导体衬底上形成高掺杂N型下部外延硅层。 在下部外延硅层上形成低掺杂P型中间外延硅层。 在中间外延硅层上形成高掺杂N型上部外延硅层。 蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。 在隔离槽内形成氧化物。 氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。 在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。 在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。 栅极导体层形成在栅极电介质层上，填充栅极沟槽。

公开(公告)号：US06440800B1

公开(公告)日：2002-08-27

申请号：US09769814

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/365 ,  H01L29/7827

摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

公开(公告)号：US06261935B1

公开(公告)日：2001-07-17

申请号：US09458725

申请日：1999-12-13

申请人： Alex See ,  Lap Chan ,  Ravi Sundaresan

发明人： Alex See ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L214763

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76895 ,  H01L29/66545 ,  H01L29/6656

摘要： A new method is provided for the creation of contact pads to the poly gate of MOS devices. STI regions are formed, layers of gate oxide, poly and SiN are deposited. The poly gate is patterned and etched leaving a layer of SiN on the surface of the gate. An oxide liner is created, an LDD implant is performed, the gate spacers are created and source/drain region implants are performed. A layer of titanium is deposited and annealed, a salicide etchback is performed to the layer of titanium creating silicided surfaces over the source and drain regions. Inter level dielectric (ILD) is deposited, the layer of ILD is polished down to the SiN layer on the top surface of the gate. The layer of SiN is removed creating a recessed gate structure. A stack of layers of titanium-amorphous silicon-titanium (Ti/Si/Ti) or a layer of WSix is deposited over the layer of ILD filling the recess on top of the gate with Ti/Si/Ti. This Ti/Si/Ti (or WSix) is patterned and etched forming a Ti/Si/Ti stack (or layer of WSix) that partially overlays the layer of ILD while also penetrating the recessed opening of the gate electrode. The layer of Ti/Si/Ti is silicided and forms the contact pad to the gate structure.

摘要翻译： 提供了一种用于向MOS器件的多晶硅栅极创建接触焊盘的新方法。 形成STI区，沉积栅氧化层，聚和SiN层。 多晶硅栅极被图案化和蚀刻，在栅极的表面上留下一层SiN层。 产生氧化物衬垫，执行LDD注入，产生栅极间隔物并执行源极/漏极区域注入。 沉积并退火一层钛，对源层和漏极区产生硅化表面的钛层进行自对准硅蚀刻蚀刻。 层间电介质（ILD）被沉积，ILD层被抛光到栅极顶表面上的SiN层。 去除SiN层，产生凹陷的栅极结构。 在TiD / Si / Ti上在栅极顶部填充凹槽的ILD层上沉积一叠钛 - 非晶硅 - 钛（Ti / Si / Ti）或一层WSix层。 该Ti / Si / Ti（或WSix）被图案化和蚀刻形成Ti / Si / Ti叠层（或WSix层），其部分覆盖ILD层，同时也穿过栅电极的凹入开口。 Ti / Si / Ti层被硅化并形成与栅极结构的接触焊盘。

公开(公告)号：US5742088A

公开(公告)日：1998-04-21

申请号：US837486

申请日：1997-04-18

申请人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

发明人： Yang Pan ,  Lap Chan ,  Ravi Sundaresan

IPC分类号： H01L21/74 ,  H01L29/08 ,  H01L27/11 ,  H01L29/40

CPC分类号： H01L21/743

摘要： A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.

摘要翻译： 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层，并被蚀刻掉以提供到衬底的开口，其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点，并提供到衬底的开口，其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉，由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层，然后各向同性地蚀刻掉，直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结，其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。

公开(公告)号：US06747314B2

公开(公告)日：2004-06-08

申请号：US10242483

申请日：2002-09-12

申请人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

发明人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

IPC分类号： H01L2976

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

公开(公告)号：US06417056B1

公开(公告)日：2002-07-09

申请号：US09981439

申请日：2001-10-18

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66636 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834

摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

摘要翻译： 描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。 栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。 在衬底上形成氧化物层。 第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。 源/漏扩展被植入。 第二间隔件形成在第一间隔件上。 源极/漏极区域被植入。 沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。 去除暴露的第二间隔物和下面的氧化物层。 蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。 微通孔填充有外延氧化物层并且平坦化到硬掩模层。 图案化电介质层以在外延氧化物层上形成第三间隔物。 微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

公开(公告)号：US06406945B1

公开(公告)日：2002-06-18

申请号：US09769810

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21335

CPC分类号： H01L29/517 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66583 ,  Y10S257/90

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成虚拟电介质层。 图案化虚拟介质层以形成栅极开口。 在虚拟电介质上和栅极开口中形成高K电介质层。 在高K电介质层上形成低K电介质层。 在栅极开口边缘的低K电介质层上形成间隔物。 低K电介质层从间隔物之间​​的栅极开口的底部去除。 移除间隔件以形成阶梯式门开口。 阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层 开门 在阶梯式门开口形成栅电极。