公开(公告)号：US06221709B1

公开(公告)日：2001-04-24

申请号：US08885636

申请日：1997-06-30

申请人： Pervez Hassan Sagarwala ,  Mehdi Zamanian ,  Ravi Sundaresan

发明人： Pervez Hassan Sagarwala ,  Mehdi Zamanian ,  Ravi Sundaresan

IPC分类号： H01L218238

CPC分类号： H01L21/823814 ,  Y10S257/90

摘要： A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device. The resulting integrated circuit has an LDD n-channel transistor and a p-channel transistor without an LDD region.

摘要翻译： 提供一种制造具有n沟道和p沟道晶体管的集成电路的方法。 该方法包括形成用于与栅电极自对准的n沟道晶体管的LDD区域。 然后在结构上形成第一氧化物，并且n型硅区域通过第一氧化物与p +型掺杂剂注入，以形成p沟道晶体管的源极和漏极区域。 在结构上形成第二氧化物。 然后蚀刻两个氧化物层以提供侧壁间隔物，其具有由第一氧化物形成的内部部分和由第二氧化物形成的外部部分。 p型硅区域注入n +型掺杂剂以形成n沟道晶体管的低电阻率区域。 在器件的进一步热处理期间，p沟道晶体管的源极和漏极中的p +注入通常在向栅极方向扩散。 所得到的集成电路具有LDD n沟道晶体管和没有LDD区的p沟道晶体管。

公开(公告)号：US06759717B2

公开(公告)日：2004-07-06

申请号：US09800039

申请日：2001-03-06

申请人： Pervez Hassan Sagarwala ,  Mehdi Zamanian ,  Ravi Sundaresan

发明人： Pervez Hassan Sagarwala ,  Mehdi Zamanian ,  Ravi Sundaresan

IPC分类号： H01L2976

CPC分类号： H01L21/823814 ,  Y10S257/90

摘要： A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device. The resulting integrated circuit has an LDD n-channel transistor and a p-channel transistor without an LDD region.

摘要翻译： 提供一种制造具有n沟道和p沟道晶体管的集成电路的方法。 该方法包括形成用于与栅电极自对准的n沟道晶体管的LDD区域。 然后在结构上形成第一氧化物，并且n型硅区域通过第一氧化物与p +型掺杂剂注入，以形成p沟道晶体管的源极和漏极区域。 在结构上形成第二氧化物。 然后蚀刻两个氧化物层以提供侧壁间隔物，其具有由第一氧化物形成的内部部分和由第二氧化物形成的外部部分。 p型硅区域注入n +型掺杂剂以形成n沟道晶体管的低电阻率区域。 在器件的进一步热处理期间，p沟道晶体管的源极和漏极中的p +注入通常在向栅极方向扩散。 所得到的集成电路具有LDD n沟道晶体管和没有LDD区的p沟道晶体管。

公开(公告)号：US06747314B2

公开(公告)日：2004-06-08

申请号：US10242483

申请日：2002-09-12

申请人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

发明人： Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

IPC分类号： H01L2976

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

公开(公告)号：US06417056B1

公开(公告)日：2002-07-09

申请号：US09981439

申请日：2001-10-18

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66636 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834

摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

摘要翻译： 描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。 栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。 在衬底上形成氧化物层。 第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。 源/漏扩展被植入。 第二间隔件形成在第一间隔件上。 源极/漏极区域被植入。 沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。 去除暴露的第二间隔物和下面的氧化物层。 蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。 微通孔填充有外延氧化物层并且平坦化到硬掩模层。 图案化电介质层以在外延氧化物层上形成第三间隔物。 微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

公开(公告)号：US06406945B1

公开(公告)日：2002-06-18

申请号：US09769810

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21335

CPC分类号： H01L29/517 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66583 ,  Y10S257/90

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成虚拟电介质层。 图案化虚拟介质层以形成栅极开口。 在虚拟电介质上和栅极开口中形成高K电介质层。 在高K电介质层上形成低K电介质层。 在栅极开口边缘的低K电介质层上形成间隔物。 低K电介质层从间隔物之间​​的栅极开口的底部去除。 移除间隔件以形成阶梯式门开口。 阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层 开门 在阶梯式门开口形成栅电极。

公开(公告)号：US06541327B1

公开(公告)日：2003-04-01

申请号：US09760123

申请日：2001-01-16

申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

IPC分类号： H01L218238

CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66575

摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.

摘要翻译： 一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。 栅极结构形成在衬底上。 栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。 在衬底和栅极结构之上形成第一绝缘层。 形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。 我们通过抗蚀剂层中的开口蚀刻绝缘层。 蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。 我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。 我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。 我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。 在栅电极，绝缘层上沉积导电层。 导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

公开(公告)号：US06436770B1

公开(公告)日：2002-08-20

申请号：US09721720

申请日：2000-11-27

申请人： Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee

发明人： Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee

IPC分类号： H01L21332

CPC分类号： H01L29/7827 ,  H01L29/42356 ,  H01L29/66666

摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.

摘要翻译： 一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。 在衬底中形成隔离区。 隔离区限定有效区域。 然后，我们在活动区域​​中形成一个源区域。 在有源区域和隔离区域上形成介电层。 我们在电介质层上形成阻挡层。 我们在屏障层形成一个开口。 在开口中形成栅极层。 我们在导电层和阻挡层上形成绝缘层。 我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。 栅极电介质隔离物形成在栅极层的侧壁上。 然后，我们形成一个填充门开口的导电塞。 绝缘层被去除。 我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。 导电插塞的其余部分包括沟道区域。 沟道长度在源极区域的顶部和漏极区域之间。 我们在阻挡层，栅极层和导电插塞上形成层间电介质层。 通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。

公开(公告)号：US06372569B1

公开(公告)日：2002-04-16

申请号：US09483035

申请日：2000-01-18

申请人： Yong Meng Lee ,  Gao Feng ,  Yunqzang Zhang ,  Ravi Sundaresan

发明人： Yong Meng Lee ,  Gao Feng ,  Yunqzang Zhang ,  Ravi Sundaresan

IPC分类号： H01L218238

CPC分类号： H01L21/823814

摘要： A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

摘要翻译： 一种在半导体器件中选择性地形成SiN层的方法，包括以下步骤。 提供具有形成在其中的至少一个PMOS晶体管和一个NMOS晶体管的半导体结构。 PMOS和NMOS晶体管各自具有源极/漏极区域，栅极和自对准硅化物接触区域。 在半导体结构和PMOS和NMOS晶体管上沉积未掺杂的硅酸盐玻璃（USG）层。 富含H 2 O的PECVD氮化硅层沉积在未掺杂的硅酸盐玻璃层上并在PMOS和NMOS晶体管之上。 从富于PMOS晶体管的图案化，蚀刻和去除富H2的PECVD氮化硅层。 在该结构上形成层间电介质（ILD）层。 ILD层被致密化，由此氢从NMOS晶体管上的富H 2 PECVD氮化硅层扩散到NMOS晶体管的源极/漏极。

公开(公告)号：US06313008B1

公开(公告)日：2001-11-06

申请号：US09768486

申请日：2001-01-25

申请人： Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee

发明人： Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.

摘要翻译： 本发明描述了形成球形STI沟槽的方法的三个实施例。 第一实施例开始于在衬底上形成阻挡层。 在阻挡层中形成隔离开口。 接下来，通过所述隔离开口将离子注入到所述衬底中，以形成Si损伤或掺杂的第一区域。 第一区域是选择性蚀刻以形成孔。 孔用绝缘材料填充以形成气球形的浅沟槽隔离（STI）区域。 衬底在所述球形浅沟槽隔离（STI）区域之间具有有效区域。 第二实施例通过在植入物之前在衬底中形成沟槽而与第一实施例不同。 在通过沟槽对衬底进行各向同性蚀刻之前，第三实施例在沟槽中形成衬垫。

公开(公告)号：US06461900B1

公开(公告)日：2002-10-08

申请号：US09981438

申请日：2001-10-18

申请人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

发明人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

IPC分类号： H01L2100

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。