公开(公告)号：US08957470B2

公开(公告)日：2015-02-17

申请号：US13526550

申请日：2012-06-19

申请人： Yan Zhe Tang ,  Shyue Seng Tan ,  Ying Keung Leung ,  Elgin Quek

发明人： Yan Zhe Tang ,  Shyue Seng Tan ,  Ying Keung Leung ,  Elgin Quek

IPC分类号： H01L29/788

CPC分类号： H01L21/82385 ,  H01L21/76224 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0928 ,  H01L27/11546

摘要： A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (TSM) is disposed in the first region. A high voltage (HV) transistor having a second stack height (TSHV) is disposed in the second region and a logic transistor having a third stack height (TSL) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate.

摘要翻译： 公开了一种用于形成装置的装置和方法。 该装置包括具有第一，第二和第三区域的基板。 第一区域包括存储单元区域，第二区域包括外围电路区域，第三区域包括逻辑区域。 包括具有第一堆叠高度（TSM）的存储晶体管的存储单元设置在第一区域中。 具有第二叠层高度（TSHV）的高压（HV）晶体管设置在第二区域中，并且具有第三叠层高度（TSL）的逻辑晶体管设置在第三区域中。 第一，第二和第三堆叠高度在基板上基本相同。

公开(公告)号：US20130334584A1

公开(公告)日：2013-12-19

申请号：US13526550

申请日：2012-06-19

申请人： Yan Zhe TANG ,  Shyue Seng TAN ,  Ying Keung LEUNG ,  Elgin QUEK

发明人： Yan Zhe TANG ,  Shyue Seng TAN ,  Ying Keung LEUNG ,  Elgin QUEK

IPC分类号： H01L29/788 ,  H01L21/76

CPC分类号： H01L21/82385 ,  H01L21/76224 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0928 ,  H01L27/11546

摘要： A device and methods for forming a device are disclosed. The device includes a substrate having first, second and third regions. The first region includes a memory cell region, the second region includes a peripheral circuit region and the third region includes a logic region. A memory cell which includes a memory transistor having a first stack height (TSM) is disposed in the first region. A high voltage (HV) transistor having a second stack height (TSHV) is disposed in the second region and a logic transistor having a third stack height (TSL) is disposed in the third region. The first, second and third stack heights are substantially the same across the substrate.

摘要翻译： 公开了一种用于形成装置的装置和方法。 该装置包括具有第一，第二和第三区域的基板。 第一区域包括存储单元区域，第二区域包括外围电路区域，第三区域包括逻辑区域。 包括具有第一堆叠高度（TSM）的存储晶体管的存储单元设置在第一区域中。 具有第二叠层高度（TSHV）的高压（HV）晶体管设置在第二区域中，并且具有第三叠层高度（TSL）的逻辑晶体管设置在第三区域中。 第一，第二和第三堆叠高度在基板上基本相同。

公开(公告)号：US20120112256A1

公开(公告)日：2012-05-10

申请号：US12925991

申请日：2010-11-04

申请人： Shyue Seng Tan ,  Ying Keung Leung ,  Elgin Quek

发明人： Shyue Seng Tan ,  Ying Keung Leung ,  Elgin Quek

IPC分类号： H01L29/68 ,  H01L21/71

CPC分类号： H01L29/42332 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： Semiconductor devices and methods of fabricating the devices are provided. An example device may include a substrate and a gate structure on the substrate. The gate structure includes a control gate having at least three distinct gate regions. First and second control gate regions are configured as a first field type, such as a high-gate or low-gate type. A third control gate region configured as a second field type (different from the first field type) is at least partially disposed between the first and second control gate regions.

摘要翻译： 提供半导体器件和制造器件的方法。 示例性器件可以包括衬底和衬底上的栅极结构。 栅极结构包括具有至少三个不同栅极区域的控制栅极。 第一和第二控制栅极区被配置为第一场类型，例如高栅极或低栅极型。 配置为第二场类型（不同于第一场类型）的第三控制栅极区域至少部分地设置在第一和第二控制栅极区域之间。

公开(公告)号：US20100237441A1

公开(公告)日：2010-09-23

申请号：US12778912

申请日：2010-05-12

申请人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlis H. Diaz

发明人： Da-Wen Lin ,  Ying-Shiou Lin ,  Shyh-Wei Wang ,  Li-Ping Huang ,  Ying-Keung Leung ,  Carlis H. Diaz

IPC分类号： H01L29/739

CPC分类号： H01L29/7391 ,  H01L29/0657 ,  H01L29/42312 ,  H01L29/66356

摘要： A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.

摘要翻译： 门控二极管半导体器件或类似部件及其制造方法。 该器件具有栅极结构，该栅极结构设置在通道上的衬底上并且与源极和漏极相邻。 源极或漏极区域或两者的顶部形成为比栅极结构的底部全部或部分更高的高度。 这种配置可以通过用引导随后的蚀刻工艺来形成倾斜轮廓的轮廓层覆盖栅极结构和衬底来实现。 如果两者都存在，则源极和漏极可以是对称的或非对称的。 这种配置显着地减少了掺杂剂的侵蚀，结果减少了结漏电。

公开(公告)号：US06709934B2

公开(公告)日：2004-03-23

申请号：US10196111

申请日：2002-07-16

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成低K电介质层。 在低K电介质层上形成虚拟电介质层。 图案化虚拟介电层和低K电介质层以形成开口。 虚拟电介质层被选择性地蚀刻到低K电介质层以形成阶梯式栅极开口。 在虚拟电介质和阶梯式门开口中形成高K电介质层。 在高K电介质层上形成栅电极。

公开(公告)号：US06511884B1

公开(公告)日：2003-01-28

申请号：US09972503

申请日：2001-10-09

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21336

CPC分类号： H01L29/66666 ,  H01L29/7827

摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.

摘要翻译： 一种制造隔离垂直晶体管的方法，包括以下步骤。 提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。 该晶片还包括在中心晶体管区域两侧的STI区域。 将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。 具有侧壁的立柱。 在晶片上形成衬垫介质层，衬在垂直柱上。 在焊盘介电层上形成氮化物层。 该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。 图案化的氮化物和焊盘介电层被去除。 去除图案化的硬掩模。 栅极氧化物生长在晶片和垂直柱的暴露部分上。 在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。 间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的 垂直晶体管。

公开(公告)号：US06417054B1

公开(公告)日：2002-07-09

申请号：US09769830

申请日：2001-01-26

申请人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

发明人： Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep

IPC分类号： H01L21366

CPC分类号： H01L29/6653 ,  H01L21/76232 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66636

摘要： A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.

摘要翻译： 一种通过在STI侧面形成沟槽并用氧化物填充沟槽，在绝缘层（氧化物）上具有升高的源极/漏极（S / D）区域的自对准TX的方法。 STI区域形成在基板中。 形成栅极结构。 在基板中与栅极结构相邻地形成LDD区域。 隔板形成在栅极结构的侧壁上。 我们蚀刻STI区域和第​​一间隔物之间​​的S / D沟槽。 S / D沟槽填充有S / D绝缘层。 在S / D绝缘层和LDD区域上形成升高的S / D区域。 在STI区域上形成顶部隔离层。 本发明在绝缘层上构建了凸起的源极/漏极（S / D）区域，并减少了结合漏电和热载流子对栅极氧化物的降解。

公开(公告)号：US06380088B1

公开(公告)日：2002-04-30

申请号：US09764241

申请日：2001-01-19

申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

IPC分类号： H01L21302

CPC分类号： H01L29/66583 ,  H01L21/76224 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4983 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636

摘要： An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

摘要翻译： 一种改进的MOS晶体管和制造改进的MOS晶体管的方法。 MOS晶体管，具有沟槽侧壁上的凹陷源极漏极，具有替代栅极技术。 在浅沟槽隔离件中形成孔，其在有源区域中暴露衬底的侧壁。 在孔的有源区域中掺杂衬底的侧壁。 然后在孔中形成导电材料，并且导电材料变成源区和漏区。 然后去除蚀刻停止层，暴露导电材料的侧壁，并且对导电材料的暴露侧壁进行氧化预处理。 垫片形成在衬垫氧化物的顶部和导电材料的氧化部分的侧壁上。 衬垫氧化物层从结构中移除，但不从衬垫下方移除。 在间隔物之间​​的有源区域中的基板上形成栅极电介质层; 并且在所述栅极电介质层上形成栅电极。

公开(公告)号：US06306715B1

公开(公告)日：2001-10-23

申请号：US09756008

申请日：2001-01-08

申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

IPC分类号： H01L21336

CPC分类号： H01L21/32136 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/6659

摘要： A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.

摘要翻译： 一种形成具有窄沟道区和宽顶（第二）栅极部分的MOS晶体管的方法。 在衬底上形成栅极介电层和第一栅极层。 第二栅极部分形成在第一栅极层上。 间隔件形成在第二栅极部分的侧壁上。 在关键步骤中，我们对第一栅极层进行各向同性蚀刻，以切割第二栅极部分以形成第一栅极部分，使得第一部分具有小于第二栅极部分的宽度。 去除间隔物。 形成轻掺杂的漏极，侧壁间隔物和源极/漏极区以完成该器件。

公开(公告)号：US06306714B1

公开(公告)日：2001-10-23

申请号：US09713802

申请日：2000-11-16

申请人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

发明人： Yang Pan ,  James Yongmeng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan

IPC分类号： H01L21336

CPC分类号： H01L21/76877 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/66583 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over the first insulating layer. Ions are implanted through the source/drain openings. A first dielectric layer is formed on the substrate in the gate opening and source/drain openings. A gate is formed in the gate opening and raised source/drain (S/D) blocks in the source/drain openings. We remove the spacer blocks to form spacer block openings. We form second LDD regions by implanting ions through the spacer block openings. We form second spacer blocks in the spacer block openings. Plug opening are formed through the raised source/drain (S/D) blocks. Contact plugs are formed in the form plug opening.

摘要翻译： 制造用于MOS器件的升高的源极/漏极（S / D）的方法。 在衬底上形成具有栅极开口和源极/漏极开口的第一绝缘层。 我们形成了在第一绝缘层上的源/漏开口上方具有开口的LDD抗蚀剂掩模。 离子通过源极/漏极开口植入。 在栅极开口和源极/漏极开口中的基板上形成第一电介质层。 栅极形成在源极/漏极开口中的栅极开路和升高的源极/漏极（S / D）块中。 我们移除间隔块以形成间隔块开口。 我们通过将离子注入间隔块开口形成第二LDD区域。 我们在间隔块开口中形成第二间隔块。 插头开口通过凸起的源极/漏极（S / D）块形成。 接触塞以形式的塞子开口形成。