公开(公告)号：US07105866B2

公开(公告)日：2006-09-12

申请号：US10911624

申请日：2004-08-05

Applicant: Nada El-Zein ,  Jamal Ramdani ,  Kurt Eisenbeiser ,  Ravindranath Droopad

Inventor： Nada El-Zein ,  Jamal Ramdani ,  Kurt Eisenbeiser ,  Ravindranath Droopad

IPC: H01L29/861

CPC classification number: H01L29/882 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract translation: 通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

公开(公告)号：US5425043A

公开(公告)日：1995-06-13

申请号：US287784

申请日：1994-08-09

Applicant: Nick Holonyak, Jr. ,  Nada El-Zein ,  Fred A. Kish

Inventor： Nick Holonyak, Jr. ,  Nada El-Zein ,  Fred A. Kish

IPC: H01L21/316 ,  H01S5/026 ,  H01S5/10 ,  H01S5/40 ,  H01S3/19

CPC classification number: H01L21/02178 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/31666 ,  H01S5/10 ,  H01S5/1021 ,  H01S5/026 ,  H01S5/1028 ,  H01S5/1071 ,  H01S5/4031 ,  H01S5/4056 ,  H01S5/4068

Abstract: In a form of the disclosure an array of coupled cavities (called minicavities) of a QWH semiconductor laser are defined by a native oxide of an aluminum-bearing III-V semiconductor material and are arranged serially end-to-end along the longitudinal direction. The native oxide confines the injected carriers and optical field within the cavities, resulting in reflection and optical feedback distributed periodically along the laser stripe. Single-longitudinal-mode operation is exhibited over an extended range. In a further form of the disclosure, two linear arrays of end-coupled minicavities are arranged side by side to obtain a two dimensional array, with resultant lateral coupling between the linear arrays. The two dimensional array exhibits mode switching and multiple switching in the light power (L) versus current (I) characteristic (L-I) with increasing current. In another form of the disclosure, a stripe laser is transversely coupled (or side-coupled) with a linear array of end-coupled minicavities. Bistability and switching are demonstrated in the light versus current (L-I) characteristic of a native-oxide-defined structure of this type. The device, with internally coupled elements and the current partitioned among the elements, exhibits a large hysteresis in the L-I curve, with switching from the stimulated to the spontaneous regime occurring over substantial power (light) and current ranges.

Abstract translation: 在本公开的形式中，QWH半导体激光器的耦合空腔（称为微小电位）的阵列由含铝III-V半导体材料的天然氧化物限定，并且沿纵向方向串联地串联设置。 天然氧化物将注入的载流子和光场限制在空腔内，导致沿着激光条带周期性地分布的反射和光学反馈。 单纵模操作在扩展范围内展现。 在本公开的另一形式中，并行布置两个端部耦合的微小的线性阵列以获得二维阵列，并且在线性阵列之间产生横向耦合。 二维阵列随着电流的增加呈现模式切换和光功率（L）与电流（I）特性（L-I）的多次切换。 在本公开的另一种形式中，条形激光器与端部耦合的微型半导体的线性阵列横向耦合（或侧耦合）。 在这种类型的自然氧化物定义的结构的光 - 电流（L-I）特性中证明了双稳态和开关。 具有内部耦合元件和在元件之间分配的电流的器件在L-I曲线中表现出大的滞后，从被激励到自发状态从基本功率（光）和电流范围发生。

公开(公告)号：US08170404B2

公开(公告)日：2012-05-01

申请号：US11579889

申请日：2005-05-17

Applicant: Nam Hung Tran ,  Dennis L. Deavenport ,  Taeho Ko ,  Nada El-Zein

Inventor： Nam Hung Tran ,  Dennis L. Deavenport ,  Taeho Ko ,  Nada El-Zein

IPC: A01G13/06 ,  B05C11/00

CPC classification number: C23C16/4482 ,  C23C16/4481

Abstract: A bubbler chamber assembly comprising one chamber or two or more chambers connected in series, all chambers being in substantially vertical orientation. A solid or liquid source of the compound is contained in the chamber or chambers. The ratio between the length of the chamber or combined length of chambers connected in series with respect to the direction of flow of the carrier gas through the chamber or chambers and the average diameter equivalent of the cross section of the chamber or chambers with respect to the direction of flow of the carrier gas through the chamber or chambers is not less than about 6:1.

Abstract translation: 一种起泡器室组件，包括一个连续串联连接的一个室或两个或多个室，所有室均处于基本垂直的方向。 化合物的固体或液体源包含在室或室中。 腔室的长度或者相对于通过室或室的载气的流动方向串联连接的室的组合长度与室或室的横截面的平均直径当量相对于 载气通过室或室的流动方向不小于约6:1。

公开(公告)号：US06594478B1

公开(公告)日：2003-07-15

申请号：US09706443

申请日：2000-11-03

Applicant: Vijay Nair ,  Nada El Zein ,  Herbert Goronkin

Inventor： Vijay Nair ,  Nada El Zein ,  Herbert Goronkin

IPC: H04B128

CPC classification number: H03D7/125

Abstract: A self oscillating mixer circuit includes a dual gate FET, an NDR device coupled to a first gate of the FET, and a first bias input circuit adapted to couple a first bias voltage across the NDR device. The first bias voltage controls operation of the NDR device within an NDR region of the V-I characteristic curve of the NDR device so that oscillations occur in the NDR device and the FET. The first bias input circuit is adjustable to adjust the applied first bias voltage so as to control frequency and amplitude of the oscillations. An RF input terminal and a second bias input circuit are coupled to supply a second bias voltage at the other gate terminal, which biases the FET at maximum gain so that RF signals applied to the RF input terminal are mixed with the oscillations.

Abstract translation: 自振荡混频器电路包括双栅极FET，耦合到FET的第一栅极的NDR器件和适于耦合NDR器件上的第一偏置电压的第一偏置输入电路。 第一偏置电压控制NDR器件在NDR器件的V-I特性曲线的NDR区域内的操作，从而在NDR器件和FET中发生振荡。 第一偏置输入电路是可调节的，以调节所施加的第一偏置电压，以便控制振荡的频率和振幅。 RF输入端子和第二偏置输入电路被耦合以在另一个栅极端子处提供第二偏置电压，其以最大增益偏置FET，使得施加到RF输入端子的RF信号与振荡混合。

公开(公告)号：US5942952A

公开(公告)日：1999-08-24

申请号：US903081

申请日：1997-07-30

Applicant: Vijay K. Nair ,  Nada El-Zein ,  Kumar Shiralagi ,  George N. Maracas ,  Herbert Goronkin

Inventor： Vijay K. Nair ,  Nada El-Zein ,  Kumar Shiralagi ,  George N. Maracas ,  Herbert Goronkin

IPC: H01L27/06 ,  H01L29/88 ,  H03B1/00 ,  H03B7/06 ,  H03B7/14

CPC classification number: H03B7/06 ,  H01L27/0605 ,  H01L29/882 ,  H03B2200/0062 ,  H03B2201/02 ,  H03B7/143

Abstract: A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.

Abstract translation: VCO包括具有与晶体管的源极端子串联耦合的多个负差分电阻器件的晶体管，其中每个器件具有负的差分电阻工作区域。 偏置电路耦合到漏极和栅极端子以及操作电压，其工作电压将振荡器设置为在负差分电阻器件中的至少一个的负差分电阻区域中工作，使得在输出端子处产生选定频率的振荡。 连接晶体管，多个N器件，DC偏置电路和工作电压，使得振荡器负差分电阻工作区域分别大于每个器件负差分工作区域的N倍。

公开(公告)号：US20050056210A1

公开(公告)日：2005-03-17

申请号：US10911624

申请日：2004-08-05

Applicant: Nada El-Zein ,  Jamal Ramdani ,  Kurt Eisenbeiser ,  Ravindranath Droopad

Inventor： Nada El-Zein ,  Jamal Ramdani ,  Kurt Eisenbeiser ,  Ravindranath Droopad

IPC: H01L21/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/88 ,  C30B1/00 ,  C30B3/00 ,  C30B5/00 ,  C30B23/00 ,  C30B25/00 ,  C30B28/02 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L29/882 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract translation: 通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。

公开(公告)号：US06590236B1

公开(公告)日：2003-07-08

申请号：US09624296

申请日：2000-07-24

Applicant: Nada El-Zein ,  Jamal Ramdani ,  Kurt Eisenbeiser ,  Ravindranath Droopad

Inventor： Nada El-Zein ,  Jamal Ramdani ,  Kurt Eisenbeiser ,  Ravindranath Droopad

IPC: H01L310328

CPC classification number: H01L21/31691 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02521 ,  Y10S438/90 ,  Y10S438/933

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. These semiconductor materials have applications involving communications with high frequency signals including intelligent transportation systems such as automobile radar systems, smart cruise control systems, collision avoidance systems, and automotive navigation systems; and electronic payment systems that use microwave or RF signals such as electronic toll payment for various transportation systems including train fares, and toll roads, parking structures, and toll bridges for automobiles.

Abstract translation: 通过首先在硅晶片上生长容纳缓冲层，可以将复合半导体材料的高质量外延层生长在大的硅晶片上。 容纳缓冲层是通过氧化硅的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 这些半导体材料具有涉及与高频信号通信的应用，包括诸如汽车雷达系统，智能巡航控制系统，防撞系统和汽车导航系统之类的智能交通系统; 以及使用微波或RF信号的电子支付系统，例如用于包括火车票价的各种交通系统的电子费用付费，以及用于汽车的收费公路，停车场和收费桥。

公开(公告)号：US06204513B1

公开(公告)日：2001-03-20

申请号：US09304410

申请日：1999-05-04

Applicant: Nada El-Zein ,  Jonathan Lewis ,  Mandar R. Deshpande

Inventor： Nada El-Zein ,  Jonathan Lewis ,  Mandar R. Deshpande

IPC: H01L2920

CPC classification number: H01L29/88

Abstract: A heterostructure interband tunneling diode includes a contact layer comprising indium gallium arsenide of a first conductivity type, an injection layer comprising indium gallium arsenide of a second conductivity type, a first doped layer of the first conductivity type positioned adjacent to the contact layer, and a second doped layer of a second conductivity type juxtaposed between the first doped layer and the injection layer, wherein at least one of the first and second tunnel barrier layers comprises indium aluminium arsenide. A second embodiment includes a doped layer of the first conductivity type positioned adjacent to the contact layer, and a barrier layer positioned adjacent to the injection layer, and a quantum well layer comprising indium gallium arsenide juxtaposed between the doped layer and the barrier layer, wherein at least one of the doped and barrier layers comprises indium aluminium arsenide.

Abstract translation: 异质结构带间隧道二极管包括包含第一导电类型的砷化铟镓的接触层，包括第二导电类型的砷化铟镓的注入层，与接触层相邻定位的第一导电类型的第一掺杂层，以及 第二导电类型的第二掺杂层并置在第一掺杂层和注入层之间，其中第一和第二隧道势垒层中的至少一个包括砷化铟铝。 第二实施例包括邻近接触层定位的第一导电类型的掺杂层和邻近注入层定位的阻挡层，以及包含掺杂层和阻挡层之间的砷化铟镓的量子阱层，其中 掺杂层和阻挡层中的至少一个包括砷化铟铝。

公开(公告)号：US20070221127A1

公开(公告)日：2007-09-27

申请号：US11579889

申请日：2005-05-17

Applicant: Nam Tran ,  Dennis Deavenport ,  Taeho Ko ,  Nada El-Zein

Inventor： Nam Tran ,  Dennis Deavenport ,  Taeho Ko ,  Nada El-Zein

IPC: C23C16/00

CPC classification number: C23C16/4482 ,  C23C16/4481

Abstract: A bubbler chamber assembly comprising one chamber or two or more chambers connected in series, all chambers being in substantially vertical orientation. A solid or liquid source of the compound is contained in the chamber or chambers. The ratio between the length of the chamber or combined length of chambers connected in series with respect to the direction of flow of the carrier gas through the chamber or chambers and the average diameter equivalent of the cross section of the chamber or chambers with respect to the direction of flow of the carrier gas through the chamber or chambers is not less than about 6:1.

Abstract translation: 一种起泡器室组件，包括一个连续串联连接的一个室或两个或多个室，所有室均处于基本垂直的方向。 化合物的固体或液体源包含在室或室中。 腔室的长度或者相对于通过室或室的载气的流动方向串联连接的室的组合长度与室或室的横截面的平均直径当量相对于 载气通过室或室的流动方向不小于约6:1。

公开(公告)号：US06255710B1

公开(公告)日：2001-07-03

申请号：US09072339

申请日：1998-05-04

Applicant: Charles E. Weitzel ,  Nada El-Zein

Inventor： Charles E. Weitzel ,  Nada El-Zein

IPC: H01L2900

CPC classification number: H01L27/0605 ,  H01L21/8221 ,  H01L21/8252 ,  H01L27/0688 ,  H01L29/7722 ,  H01L29/8083

Abstract: An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.

Abstract translation: 一种集成智能电力电路，包括制造在导电基板上的功率半导体器件，源极位于基板的上表面附近，上表面和下表面之间的控制端子以及位于基板下表面附近的漏极。 在基板的上表面的一部分上形成高电阻层，直接覆盖或邻近功率器件，并且掺杂的半导体材料位于高电阻层上。 在掺杂半导体材料中形成控制电路。 可以通过在AlAs上生长一层AlAs和生长掺杂层来方便地形成高电阻层。 此后，AlAs容易氧化。