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    Non-volatile memory device, memory system, and methods of operating the device and system
    2.
    发明授权
    Non-volatile memory device, memory system, and methods of operating the device and system 有权

    公开(公告)号：US09672931B2

    公开(公告)日：2017-06-06

    申请号：US14995534

    申请日：2016-01-14

    申请人： Seok-Min Yoon ,  Myung-Hoon Choi

    发明人： Seok-Min Yoon ,  Myung-Hoon Choi

    IPC分类号： G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/14

    CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344

    摘要： Provided is a method of operating a non-volatile memory device including a plurality of strings, each string including a plurality of memory cells vertically stacked on a substrate. The method includes performing an erase operation on memory cells corresponding to a plurality of string selection lines, performing an erase verification operation on first strings connected to a first string selection line from among the plurality of string selection lines, storing fail column information corresponding to a first fail string, which is erase-failed, from among the first strings, and performing an erase verification operation on second strings connected to a second string selection line from among the plurality of string selection lines, when the first strings are erase-passed.

    NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件和包含非易失性存储器件的存储器件

    公开(公告)号：US20160343444A1

    公开(公告)日：2016-11-24

    申请号：US14964056

    申请日：2015-12-09

    申请人： JONG-CHUL PARK ,  SEUNG-BUM KIM ,  MYUNG-HOON CHOI

    发明人： JONG-CHUL PARK ,  SEUNG-BUM KIM ,  MYUNG-HOON CHOI

    IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/08

    CPC分类号： G11C16/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3477

    摘要： A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

    摘要翻译： 非易失性存储器件包括具有存储单元的存储单元阵列，通过字线连接到存储单元的行解码器电路，通过位线连接到存储单元的页缓冲器电路，以及控制行解码器电路和 页面缓冲器电路，以重复执行包括相对于存储器单元的擦除和擦除验证的擦除循环。 控制电路被配置为根据当前擦除环路的擦除验证的结果来选择擦除电压的增加和减少中的一个，并且在随后的擦除环路的擦除操作中将控制的擦除电压施加到存储器单元 。

    MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE
    5.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF CONTROLLING READ VOLTAGE OF THE MEMORY DEVICE 有权
    存储器件，存储器系统和控制存储器件读取电压的方法

    公开(公告)号：US20150029796A1

    公开(公告)日：2015-01-29

    申请号：US13948557

    申请日：2013-07-23

    申请人： MYUNG-HOON CHOI ,  JAE-YONG JEONG ,  KI-TAE PARK

    发明人： MYUNG-HOON CHOI ,  JAE-YONG JEONG ,  KI-TAE PARK

    IPC分类号： G11C7/10 ,  G11C29/44

    CPC分类号： G11C7/1057 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44

    摘要： A memory device includes a memory cell array having a plurality of memory cells, and a page buffer unit including a plurality of page buffers configured to store a plurality of pieces of data sequentially read from some of the plurality of memory cells at different read voltage levels, respectively, and to perform a logic operation on the plurality of pieces of data, respectively. The memory device further includes a counting unit configured to count the number of memory cells that exist in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation

    摘要翻译： 存储器件包括具有多个存储器单元的存储单元阵列，以及一个页缓冲器单元，包括多个页缓冲器，其被配置为存储从不同读电压电平的多个存储单元中的一些存储单元顺序读取的多个数据段 分别对多条数据执行逻辑运算。 存储装置还包括计数单元，其被配置为基于逻辑运算的结果对存在于由不同读取电压电平定义的多个部分中的每一个中存储的存储器单元的数量进行计数

    NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF DRIVING THE SAME 有权
    非易失性存储器件及其驱动方法

    公开(公告)号：US20120257452A1

    公开(公告)日：2012-10-11

    申请号：US13432149

    申请日：2012-03-28

    申请人： JONG-YOUNG KIM ,  MYUNG-HOON CHOI

    发明人： JONG-YOUNG KIM ,  MYUNG-HOON CHOI

    IPC分类号： G11C16/04

    CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

    摘要： A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.

    摘要翻译： 非易失性存储器件包括多个存储器块，以及传输晶体管阵列，其响应于块选择信号将多个驱动信号传输到多个存储器块中的所选择的存储器块。 传输晶体管阵列包括高压晶体管，其包括一个公共漏极和形成在一个有源区域中的两个源极，并且传输到公共漏极的多个驱动信号中的一个驱动信号通过两个源发送到不同的存储器块。

    NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND METHODS OF OPERATING THE DEVICE AND SYSTEM
    9.
    发明申请
    NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND METHODS OF OPERATING THE DEVICE AND SYSTEM 有权
    非易失性存储器件，存储器系统以及操作器件和系统的方法

    公开(公告)号：US20160260496A1

    公开(公告)日：2016-09-08

    申请号：US14995534

    申请日：2016-01-14

    申请人： SEOK-MIN YOON ,  MYUNG-HOON CHOI

    发明人： SEOK-MIN YOON ,  MYUNG-HOON CHOI

    IPC分类号： G11C16/34 ,  G11C16/14 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344

    摘要： Provided is a method of operating a non-volatile memory device including a plurality of strings, each string including a plurality of memory cells vertically stacked on a substrate. The method includes performing an erase operation on memory cells corresponding to a plurality of string selection lines, performing an erase verification operation on first strings connected to a first string selection line from among the plurality of string selection lines, storing fail column information corresponding to a first fail string, which is erase-failed, from among the first strings, and performing an erase verification operation on second strings connected to a second string selection line from among the plurality of string selection lines, when the first strings are erase-passed.

    摘要翻译： 提供了一种操作包括多个串的非易失性存储器件的方法，每个串包括垂直堆叠在衬底上的多个存储单元。 该方法包括对与多个串选择行相对应的存储单元执行擦除操作，对从多个字符串选择行中连接到第一字符串选择行的第一字符串执行擦除验证操作，存储对应于 当第一串被擦除通过时，对从第一串中的第一串选择线连接到第二串选择线的第二串进行擦除验证操作，该擦除验证操作是擦除失败的。