公开(公告)号：US20130119478A1

公开(公告)日：2013-05-16

申请号：US13481803

申请日：2012-05-26

申请人： MIENO FUMITAKE

发明人： MIENO FUMITAKE

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices.

摘要翻译： 半导体器件被描述为包括具有由第一半导体材料形成的层的第一鳍片和由第二半导体材料形成的第二鳍片。 第一和第二半导体材料是不同的。 第二半导体材料可以具有大于第一半导体材料的P型载流子的迁移率的P型载流子的迁移率。 第二鳍包括由第二半导体材料形成的层下面的第一半导体材料形成的层。 半导体器件还包括设置在第一和第二鳍片上的硬掩模层和设置在第一鳍片和第二鳍片下方的绝缘体层。 第一和第二半导体材料分别包括硅和锗。 第一和第二鳍用于形成相应的N沟道和P沟道半导体器件。

公开(公告)号：US20120091462A1

公开(公告)日：2012-04-19

申请号：US13332259

申请日：2011-12-20

申请人： MIENO FUMITAKE

发明人： MIENO FUMITAKE

IPC分类号： H01L29/786

CPC分类号： H01L29/792 ,  H01L27/1203 ,  H01L29/66833

摘要： A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P− polysilicon layer; and at least one control gate overlying the ONO layer. The control gate may be made of a metal layer or a P+ polysilicon layer.

摘要翻译： 具有薄膜晶体管（TFT）金属氧化物 - 氮化物 - 氧化物半导体（MONOS）或半导体 - 氧化物 - 氧化物 - 氧化物半导体（SONOS）存储单元结构的器件包括衬底，衬底上的电介质层和 一个或多个源极或漏极区域被嵌入在电介质层中。 电介质层与第一表面相关联。 所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。 另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P多晶硅层上的氧化物 - 氮化物 - 氧化物（ONO）层; 以及覆盖ONO层的至少一个控制门。 控制栅极可以由金属层或P +多晶硅层制成。

公开(公告)号：US20110140192A1

公开(公告)日：2011-06-16

申请号：US12969563

申请日：2010-12-15

申请人： MIENO FUMITAKE

发明人： MIENO FUMITAKE

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7887 ,  H01L21/28114 ,  H01L29/40114 ,  H01L29/66825

摘要： A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material.

摘要翻译： 提供了一种形成双位单元结构的方法。 该方法包括提供包括表面区域的半导体衬底。 形成覆盖在表面区域上的栅介质层。 该方法形成覆盖栅极电介质层的多晶硅栅极结构。 在具体实施例中，该方法使栅极多晶硅结构进入氧化环境，以形成覆盖栅极多晶硅结构的第一氧化硅层。 优选地，在栅极多晶硅结构下方形成底切区域。 该方法包括形成覆盖多晶硅栅极结构的未掺杂多晶硅材料，该多晶硅栅极结构包括底切区域和栅极介电层。 对未掺杂的多晶硅材料进行选择性蚀刻处理，以在底切区域的一部分中形成插入区域，同时插入区域保持填充未掺杂的多晶硅材料。

公开(公告)号：US20110140190A1

公开(公告)日：2011-06-16

申请号：US12965808

申请日：2010-12-10

申请人： MIENO FUMITAKE

发明人： MIENO FUMITAKE

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/28114 ,  H01L29/66833 ,  H01L29/7923

摘要： A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure.

摘要翻译： 制造具有氧化铝材料的双位单元结构的方法包括形成覆盖在半导体衬底上的栅极介电层和覆盖栅极电介质层的多晶硅栅极结构。 在多晶硅栅极结构下面的栅极电介质层的每一侧形成底切区域。 此后，进行氧化处理以在多晶硅栅极结构的外围表面上形成第一氧化硅层，并在半导体衬底的暴露表面上形成第二氧化硅层。 然后，在包括底切区域和栅极介电层的第一和第二氧化硅层上沉积氧化铝材料。 选择性地蚀刻氧化铝材料以在底切区域的一部分中形成插入区域。 形成侧壁间隔物以隔离和保护暴露的氧化铝材料和多晶硅栅极结构。

公开(公告)号：US08716080B2

公开(公告)日：2014-05-06

申请号：US13481803

申请日：2012-05-26

申请人： Mieno Fumitake

发明人： Mieno Fumitake

IPC分类号： H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device is described as including a first fin having a layer formed of a first semiconductor material and a second fin that is formed of a second semiconductor material. The first and second semiconductor materials are different. The second semiconductor material may have a mobility of P-type carriers that is greater than a mobility of P-type carriers of the first semiconductor material. The second fin includes a layer formed of the first semiconductor material below the layer formed of the second semiconductor material. The semiconductor device further includes a hard mask layer disposed on the first and second fins and an insulator layer disposed below the first and second fins. The first and second semiconductor materials include silicon and germanium, respectively. The first and second fins are used to form respective N-channel and a P-channel semiconductor devices.

摘要翻译： 半导体器件被描述为包括具有由第一半导体材料形成的层的第一鳍片和由第二半导体材料形成的第二鳍片。 第一和第二半导体材料是不同的。 第二半导体材料可以具有大于第一半导体材料的P型载流子的迁移率的P型载流子的迁移率。 第二鳍包括由第二半导体材料形成的层下面的第一半导体材料形成的层。 半导体器件还包括设置在第一和第二鳍片上的硬掩模层和设置在第一鳍片和第二鳍片下方的绝缘体层。 第一和第二半导体材料分别包括硅和锗。 第一和第二鳍用于形成相应的N沟道和P沟道半导体器件。

公开(公告)号：US20130334607A1

公开(公告)日：2013-12-19

申请号：US13724284

申请日：2012-12-21

申请人： MIENO FUMITAKE ,  MEISHENG ZHOU

发明人： MIENO FUMITAKE ,  MEISHENG ZHOU

IPC分类号： H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L29/0649

摘要： A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure.

摘要翻译： 提供了制造半导体结构的方法。 该方法包括提供具有第一区域和相邻第二区域的半导体衬底，并且蚀刻半导体衬底以在第一区域中形成多个第一沟槽和在第二区域中形成第二沟槽。 鳍形成在相邻的第一沟槽之间。 第二沟槽的宽度大于第一沟槽的宽度。 该方法还包括用第一隔离材料填充第一沟槽以形成第一日照结构，并在第二沟槽内形成侧壁间隔物。 此外，该方法包括通过使用侧壁间隔物作为蚀刻掩模蚀刻在第二沟槽的底部上的暴露的半导体衬底，在第二沟槽中形成第三沟槽，并且使用第二隔离材料填充第二沟槽和第三沟槽 形成第二隔离结构。

公开(公告)号：US08569757B2

公开(公告)日：2013-10-29

申请号：US13333994

申请日：2011-12-21

申请人： Mieno Fumitake

发明人： Mieno Fumitake

IPC分类号： H01L29/04

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L27/12 ,  H01L29/8616

摘要： A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 具有非晶硅（a-Si）金属 - 氧化铝半导体（MAS）存储单元结构的半导体器件。 该器件包括衬底，覆盖在衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域，其中n型a-Si的共面表面和电介质层。 另外，器件包括p-i-n a-Si二极管结。 该器件还包括在a-Si p-i-n二极管结上的氧化铝电荷俘获层和覆盖氧化铝层的金属控制栅极。 提供了一种用于制造a-Si MAS存储单元结构并且可以重复三维地集成结构的方法。

公开(公告)号：US08546224B2

公开(公告)日：2013-10-01

申请号：US12965808

申请日：2010-12-10

申请人： Mieno Fumitake

发明人： Mieno Fumitake

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L21/28114 ,  H01L29/66833 ,  H01L29/7923

摘要： A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure.

摘要翻译： 制造具有氧化铝材料的双位单元结构的方法包括形成覆盖在半导体衬底上的栅极介电层和覆盖栅极电介质层的多晶硅栅极结构。 在多晶硅栅极结构下面的栅极电介质层的每一侧形成底切区域。 此后，进行氧化处理以在多晶硅栅极结构的外围表面上形成第一氧化硅层，并在半导体衬底的暴露表面上形成第二氧化硅层。 然后，在包括底切区域和栅极介电层的第一和第二氧化硅层上沉积氧化铝材料。 选择性地蚀刻氧化铝材料以在底切区域的一部分中形成插入区域。 形成侧壁间隔物以隔离和保护暴露的氧化铝材料和多晶硅栅极结构。

公开(公告)号：US20130134488A1

公开(公告)日：2013-05-30

申请号：US13552446

申请日：2012-07-18

申请人： Mieno Fumitake

发明人： Mieno Fumitake

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/098 ,  H01L21/26586 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0657 ,  H01L29/66901 ,  H01L29/785 ,  H01L29/808

摘要： A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

摘要翻译： 提供了一种半导体器件及其制造方法。 翅片半导体器件包括形成在衬底上的翅片和形成在衬底上并围绕翅片的绝缘材料层。 翅片具有半导体层，该半导体层具有源极区部分和漏极区域部分。 翅片包括第一通道控制区域，第二通道控制区域和两个通道控制区域之间的通道区域，它们都位于源极区域部分和漏极区域部分之间。 两个通道控制区域可以具有与通道区域不同的导电类型。

公开(公告)号：US20110156123A1

公开(公告)日：2011-06-30

申请号：US12978346

申请日：2010-12-23

申请人： MIENO FUMITAKE

发明人： MIENO FUMITAKE

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/42348 ,  G11C16/0441 ,  H01L29/40117

摘要： A method for manufacturing a twin bit cell structure of with a hafnium oxide material includes providing a semiconductor substrate having a surface region and forming a gate dielectric layer overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer and subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure. The method forms an undercut region underneath the polysilicon gate structure and subjects the polysilicon gate structure to an oxidization environment. Thereafter, the method forms a hafnium oxide material overlying the polysilicon gate structure including the undercut region and exposed portions of the gate dielectric layer. The hafnium oxide material is then selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed hafnium oxide material.

摘要翻译： 制造具有氧化铪材料的双位单元结构的方法包括提供具有表面区域并形成覆盖在表面区域上的栅极电介质层的半导体衬底。 该方法形成覆盖栅极电介质层的多晶硅栅极结构，并使多晶硅栅极结构受到氧化环境，以形成覆盖多晶硅栅极结构的第一氧化硅层。 该方法在多晶硅栅极结构下形成底切区域，并使多晶硅栅极结构受到氧化环境的影响。 此后，该方法形成覆盖多晶硅栅极结构的氧化铪材料，该多晶硅栅极结构包括底切区域和栅极电介质层的暴露部分。 然后选择性地蚀刻氧化铪材料以在底切区域的一部分中形成插入区域。 形成侧壁间隔物以隔离和保护暴露的氧化铪材料。