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    Apparatus and Method for Increasing Bandwidths of Stacked Dies
    1.
    发明申请
    Apparatus and Method for Increasing Bandwidths of Stacked Dies 有权
    用于增加堆叠模具带宽的装置和方法

    公开(公告)号：US20120250286A1

    公开(公告)日：2012-10-04

    申请号：US13077654

    申请日：2011-03-31

    Applicant: Shyh-An Chi ,  Mark Shane Peng

    Inventor： Shyh-An Chi ,  Mark Shane Peng

    IPC: H05K7/02

    CPC classification number: H01L23/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572

    Abstract: A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.

    Abstract translation: 封装结构包括彼此相同的多个管芯托架。 多个裸片载体中的每一个中的相应特征垂直地叠加在多个模具载体中的其它模具载体中的相应特征。 多个管芯载体中的每一个都包括多个包括多个数据总线的穿通基板通路（TSV）。 多个管芯载体通过多个TSV堆叠并彼此电连接。 封装结构还包括多个器件管芯。 多个器件管芯中的每一个被结合到多个管芯载体中的一个。 多个数据总线中的每一个被配置为专用于多个器件管芯之一的数据传输。

    Clocking architecture in stacked and bonded dice
    4.
    发明授权
    Clocking architecture in stacked and bonded dice 有权
    时钟结构在堆叠和保税骰子

    公开(公告)号：US07989226B2

    公开(公告)日：2011-08-02

    申请号：US12953202

    申请日：2010-11-23

    Applicant: Mark Shane Peng

    Inventor： Mark Shane Peng

    IPC: H01L21/00

    CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552

    Abstract: A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network.

    Abstract translation: 提供了一种用于在整个集成电路中分配时钟信号的方法和装置。 实施例包括分配管芯，其分别包含时钟信号分配网络或时钟信号分配网络与时钟信号发生器串联。 分配管芯通过诸如微灌电路的接口技术电连接，以将时钟信号路由到单独功能管芯上的功能电路。 或者，分配管芯可以一次电连接到多个管芯，使用通过分布管芯的通孔将时钟信号路由到不同的管芯。 这种单独的分配管芯减少了线路之间的耦合，并且还有助于在信号移动通过配电网络时防止信号偏斜。

    Design techniques for stacking identical memory dies
    6.
    发明授权
    Design techniques for stacking identical memory dies 有权
    堆叠相同内存模块的设计技术

    公开(公告)号：US07494846B2

    公开(公告)日：2009-02-24

    申请号：US11716104

    申请日：2007-03-09

    Applicant: Chao-Shun Hsu ,  Louis Liu ,  Clinton Chao ,  Mark Shane Peng

    Inventor： Chao-Shun Hsu ,  Louis Liu ,  Clinton Chao ,  Mark Shane Peng

    IPC: H01L21/8242

    CPC classification number: G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

    Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.

    Abstract translation: 半导体结构包括与第一半导体管芯相同的第一半导体管芯和第二半导体管芯。 第一半导体管芯包括第一识别电路; 以及在第一半导体管芯的表面上的第一多个输入/输出（I / O）焊盘。 第二半导体管芯包括第二识别电路，其中第一和第二识别电路被编程为彼此不同; 以及在第二半导体管芯的表面上的第二多个I / O焊盘。 第一组多个I / O焊盘中的每一个垂直对准并连接到相应的第二多个I / O焊盘之一。 第二半导体管芯垂直对齐并接合在第一半导体管芯上。

    Bandgap reference apparatus and methods
    8.
    发明授权
    Bandgap reference apparatus and methods 有权

    公开(公告)号：US09958895B2

    公开(公告)日：2018-05-01

    申请号：US13004617

    申请日：2011-01-11

    Applicant: Chih-Chia Chen ,  Mark Shane Peng

    Inventor： Chih-Chia Chen ,  Mark Shane Peng

    IPC: G05F1/10 ,  G05F3/02 ,  G05F3/30

    CPC classification number: G05F3/30

    Abstract: Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.

    Bandgap Reference Apparatus and Methods
    10.
    发明申请
    Bandgap Reference Apparatus and Methods 有权
    带隙参考装置和方法

    公开(公告)号：US20120176186A1

    公开(公告)日：2012-07-12

    申请号：US13004617

    申请日：2011-01-11

    Applicant: Chih-Chia Chen ,  Mark Shane Peng

    Inventor： Chih-Chia Chen ,  Mark Shane Peng

    IPC: G05F3/16

    CPC classification number: G05F3/30

    Abstract: Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.

    Abstract translation: 补偿带隙参考电路的结构和方法。 具有非零温度系数的第一带隙基准电路的第一集成电路管芯; 并具有第一输出参考信号，第二集成电路管芯具有第二带隙基准电路，其具有与第一带隙基准电路的温度系数相反极性的非零温度系数，并具有第二输出参考电压 提供信号; 设置在第一和第二集成电路管芯中的至少一个的加法器电路组合第一和第二输出参考信号，并输出组合的参考信号; 并且提供用于将第一和第二输出信号连接到加法器电路的连接器。 公开了用于将集成电路管芯与带隙参考电路配对并耦合模具以形成温度补偿信号的方法。

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