Charge coupled semiconductor device with dynamic control
    1.
    发明授权
    Charge coupled semiconductor device with dynamic control 失效
    电荷耦合半导体器件具有动态控制

    公开(公告)号:US4677650A

    公开(公告)日:1987-06-30

    申请号:US616936

    申请日:1984-06-07

    摘要: In a CCD, especially in an image sensor device, the information density can be doubled by sequentially switching the electrodes between a clock signal and a reference signal. Clock signals and reference signals are obtained as output signals of a shift register controlled by a monophase or multiphase clock. The register is provided, for example, using C-MOS technology. Information at the input terminal of the first stage of the shift register in combination with clock pulse signals at the register clock, determine the output signals of the next stage of the shift register. Hence, these input signals determine the voltage variations at the electrodes connected to the outputs of the register stages.

    摘要翻译: 在CCD中,特别是在图像传感器装置中,通过在时钟信号和参考信号之间顺序地切换电极,信息密度可以加倍。 获得时钟信号和参考信号作为由单相或多相时钟控制的移位寄存器的输出信号。 例如,使用C-MOS技术提供寄存器。 信号在移位寄存器的第一级的输入端与寄存器时钟的时钟脉冲信号相结合,确定移位寄存器的下一级的输出信号。 因此,这些输入信号确定连接到寄存器级的输出的电极处的电压变化。

    Charge transfer device having a subdivided channel output region
    2.
    发明授权
    Charge transfer device having a subdivided channel output region 失效
    具有细分通道输出区域的电荷转移装置

    公开(公告)号:US4649554A

    公开(公告)日:1987-03-10

    申请号:US819989

    申请日:1986-01-15

    CPC分类号: G11C27/04 G11C19/285

    摘要: In a charge transfer device in accordance with the invention, the channel is subdivided at the area of the output into two subchannels provided with separate output gates which are clocked in phase opposition, and with separate reset gates which are likewise clocked in phase opposition. Between the output gates and the reset gates there is arranged a floating gate common to both subchannels by which signals can be read during 100% of a clock period so that no additional filtering operations for filtering out spectra of higher order are required. This output circuit can be used in applications in which high speeds and a high sensitivity are required.

    摘要翻译: 在根据本发明的电荷转移装置中,通道在输出的区域被细分为两个子通道,分成两个子通道,这两个子通道具有相位相反的时钟脉冲的单独的输出门,并且具有相同时钟相位的单独的复位门。 在输出门和复位门之间布置有两个子通道共用的浮动栅极,通过该浮动栅极可以在100%的时钟周期内读取信号,因此不需要用于滤除高阶光谱的附加滤波操作。 该输出电路可用于需要高速度和高灵敏度的应用中。

    Bulk channel CCD with switchable draining of minority charge carriers
    8.
    发明授权
    Bulk channel CCD with switchable draining of minority charge carriers 失效
    散装通道CCD,可切换排放少数电荷载体

    公开(公告)号:US4207477A

    公开(公告)日:1980-06-10

    申请号:US913444

    申请日:1978-06-07

    摘要: The invention relates to a charge-coupled device in which the charge transport in the form of majority charge carriers takes place mainly via the bulk of a semiconductor layer of one conductivity type. The semiconductor layer has zones of the second conductivity type which do not have an electric contact but which are electrically biased by means of the isolation zone surrounding the semiconductor layer which can be connected to the zones by induction by means of the electrodes and forms a drain for charge carriers from the zones. In an embodiment the device is formed by a two-phase charge-coupled device in which the zones serve to obtain asymmetry in the system. In another embodiment the device is a series-parallel-series multiplex CCD in which the zones form isolation zones between the parallel lines.

    摘要翻译: 本发明涉及一种电荷耦合器件,其中大部分电荷载流子形式的电荷传输主要通过一种导电类型的半导体层的主体进行。 半导体层具有第二导电类型的区域,该区域不具有电接触,而是通过围绕半导体层的隔离区进行电偏置,该隔离区可以通过电极的感应连接到该区域并形成漏极 用于来自区域的电荷载体。 在一个实施例中,器件由两相电荷耦合器件形成,其中这些区域用于在系统中获得不对称性。 在另一个实施例中,该装置是串并联系列多路CCD,其中这些区在平行线之间形成隔离区。

    Accordion-type charge-coupled devices
    9.
    发明授权
    Accordion-type charge-coupled devices 失效
    手风琴式电荷耦合器件

    公开(公告)号:US4903284A

    公开(公告)日:1990-02-20

    申请号:US123697

    申请日:1987-11-23

    CPC分类号: H04N3/1543 G11C27/04

    摘要: The invention relates to a charge-coupled device of the accordion type provided with a shift register for supplying accordion clock voltages on the one hand and with clock lines for supplying conventiional clock voltages on the other hand. The electrodes are alternatively coupled to the shift register and to the clock lines. The dissipation can be considerably reduced in this device. Moreover, the transport direction can be reversed in a simple manner, which is of importance, for example, in image sensors for smear suppression.

    Circuit for converting a colour television time division multiplex
signal into simultaneous signals
    10.
    发明授权
    Circuit for converting a colour television time division multiplex signal into simultaneous signals 失效
    用于将彩色电视时分复用信号转换成同步信号的电路

    公开(公告)号:US4730209A

    公开(公告)日:1988-03-08

    申请号:US833632

    申请日:1986-02-27

    IPC分类号: H04N11/22 H04N11/12

    CPC分类号: H04N11/22

    摘要: A color television Y/U/V luminance-chrominance multiplex signal with signals which may or may not be compressed in time comprises for a television line the associated luminance information Y and half the chrominance information U or V. As a result the circuit should supply the chrominance information directly (U, V) and repeatedly (U', V') during a subsequent television line. To avoid the use of an accurate, expensive delay device having a line period delay, the circuit includes an input shift register (A) of the series-in, parallel-out type, which is coupled through an on-off switch circuit (B1, B2) to parallel inputs of two shift registers (C1, C2) of the parallel-in, series-out type. During a line blanking period (THB) writing is effected from the input shift register in the output shift registers and during two subsequent line scan periods (THS1, THS2) reading is effected consecutively therefrom. Reading may be effected in opposite phase if a repetition is to be effected after exactly one line period.

    摘要翻译: 具有可能或可能不被压缩的信号的彩色电视Y / U / V亮度色度多路复用信号包括对于电视线,相关联的亮度信息Y和色度信息U或V的一半。因此,电路应该提供 在随后的电视线中直接(U,V)和色度信息(U',V')。 为了避免使用具有线路周期延迟的精确,昂贵的延迟装置,电路包括串联并联输出型的输入移位寄存器(A),其通过开 - 关开关电路(B1 ,B2)到并联串联输出类型的两个移位寄存器(C1,C2)的并行输入。 在行消隐期间(THB)中,从输出移位寄存器中的输入移位寄存器进行写入,并且在两个后续行扫描周期(THS1,THS2)期间连续执行读取。 如果在完全一个行周期之后进行重复,则可以在相反的阶段进行读取。