公开(公告)号：US5374834A

公开(公告)日：1994-12-20

申请号：US134965

申请日：1993-10-12

Applicant: Michael W. Geis ,  Stephanie A. Gajar ,  Nancy Geis

Inventor： Michael W. Geis ,  Stephanie A. Gajar ,  Nancy Geis

IPC: B03C5/02 ,  G01N27/447 ,  H01L29/78

CPC classification number: G01N27/44752 ,  B03C5/026 ,  B03C5/028 ,  Y10S257/912

Abstract: An ionic liquid-channel charge-coupled device that separates ions in a liquid sample according to ion mobility characteristics includes a channel having an inner wall that has a matrix liquid disposed within. An insulating material surrounds the channel, and an introduction element introduces a liquid sample into the channel. The sample is preferably a liquid solution that has at least one ionic specie present in the solution. The device further includes a gating element that establishes at least one charge packet in the channel in response to an externally applied input sisal, and a transport element that induces the charge packet to migrate through the channel. The gate element can be a plurality of spaced-apart, electrically conductive, gate structures that are alternately disposable between a high voltage state and a low voltage state. The transport element further includes an application element that applies a variable voltage to the gating element. This application of voltage induces the charge packets to form under the gate structures and, when the voltage applied to an adjacent gate has a higher potential, induces the packet to migrate through the channel in that direction.

Abstract translation: 根据离子迁移率特性分离液体样品中的离子的离子液体通道电荷耦合器件包括具有设置在其内的基质液体的内壁的通道。 绝缘材料围绕通道，引入元件将液体样品引入通道。 样品优选是溶液中存在至少一种离子物质的液体溶液。 该装置还包括门控元件，其响应于外部施加的输入剑麻建立信道中的至少一个充电分组，以及诱导电荷分组迁移通过该信道的传输元件。 栅极元件可以是多个间隔开的导电的栅极结构，其在高电压状态和低电压状态之间交替地是一次性的。 运输元件还包括向选通元件施加可变电压的应用元件。 这种电压的应用引起电荷分组形成在栅极结构之下，并且当施加到相邻栅极的电压具有较高电位时，引起分组沿着该方向迁移通过通道。

公开(公告)号：US5086328A

公开(公告)日：1992-02-04

申请号：US474700

申请日：1990-02-02

Applicant: Ichiro Kasai ,  Richard M. Wallach ,  Bonnie A. Baumgratz ,  Michael E. Boyd

Inventor： Ichiro Kasai ,  Richard M. Wallach ,  Bonnie A. Baumgratz ,  Michael E. Boyd

IPC: H01L21/316 ,  H01L21/473

CPC classification number: H01L21/02241 ,  H01L21/02258 ,  H01L21/31679 ,  H01L21/473 ,  Y10S257/912

Abstract: A method is disclosed for passivating infrared detector arrays 50. A wafer 48 of indium antimonide (InSb) is subjected an anodization process while being illuminated by a bright incandescent lamp 66. In one embodiment, the photo-anodized layer 72 is used in an array 50 to passivate implanted diode regions 76,78 on the front side thereof, while employing an antireflective coating 74 on the backside anodized surface 70.

Abstract translation: 公开了用于钝化红外检测器阵列50的方法。在由白炽灯66照明的同时，锑化锑（InSb）的晶片48进行阳极氧化处理。在一个实施例中，光阳极氧化层72以阵列 50，以在背面阳极氧化表面70上使用抗反射涂层74，钝化其前侧的注入二极管区域76,78。

公开(公告)号：US4814292A

公开(公告)日：1989-03-21

申请号：US67412

申请日：1987-06-19

Applicant: Masayoshi Sasaki ,  Teruo Katoh

Inventor： Masayoshi Sasaki ,  Teruo Katoh

IPC: H01L21/20 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/32

CPC classification number: H01L29/66757 ,  H01L21/2022 ,  Y10S257/912

Abstract: In a process of fabricating a semiconductor device, an amorphous semiconductor layer is formed on a substrate, densified by heat-treatment, and is subjected to further heat-treatment to be changed into a polycrystalline semiconductor layer. A MOS transistor can be formed using the polycrystalline semiconductor layer.

Abstract translation: 在制造半导体器件的过程中，在基板上形成非晶半导体层，通过热处理致密化，并进一步进行热处理以变为多晶半导体层。 可以使用多晶半导体层形成MOS晶体管。

公开(公告)号：US3896484A

公开(公告)日：1975-07-22

申请号：US43986574

申请日：1974-02-06

Applicant: NISHIZAWA JUNICHI ,  NONAKA TERMUMOTO

Inventor： NISHIZAWA JUN-ICHI ,  NONAKA TERMUMOTO

IPC: G11C19/28 ,  G11C27/04 ,  H01L29/10 ,  H01L29/768 ,  H01L11/14

CPC classification number: H01L29/76883 ,  G11C19/282 ,  G11C27/04 ,  H01L29/1062 ,  H01L29/1091 ,  Y10S257/912

Abstract: A semiconductor data transmission device having an MIS structure including an intrinsic semiconductor and a plurality of metallic electrodes disposed in a predetermined pattern on its insulating layer. One of the electrodes serves as a gate electrode for injecting both groups of positive polarity carriers and groups of negative polarity carriers successively into the semiconductor and the remaining electrodes are interconnected by a time delay line. A pulse is applied to one end of the time delay line connected to that electrode nearest to the gate electrode to simultaneously transfer those groups of positive carriers and those groups of negative carriers injected into the semiconductor. A low frequency voltage is supplied to a particular one of the electrode to form carriers opposite in polarity from the moved carriers below it to extinguish the latter through the recombination.

公开(公告)号：US3745427A

公开(公告)日：1973-07-10

申请号：US3745427D

申请日：1972-03-30

Applicant: SECR DEFENCE

Inventor： HILSUM C ,  REES H

IPC: C01B25/08 ,  H01L29/201 ,  H01L47/00 ,  H01L11/00 ,  H01L15/00

CPC classification number: H01L29/201 ,  C01B25/088 ,  H01L47/00 ,  Y10S148/065 ,  Y10S257/912

Abstract: A semiconductor material having the composition InPxAs1 x where x denotes the atomic fraction of phosphorus and lies between 0.16 and 0.65 or In1 yGayAs where y denotes the atomic fraction of gallium and lies between 0.15 and 0.43. The material may be used as a basis for a Rees diode, in which a body of extrinsic semiconductor material of the conductivity type in which the minority carriers produce avalanche multiplication at lower electric field strengths than do the majority carriers has formed on it a first heavily doped electrode of the same conductivity type as the body and a second heavily doped electrode.

公开(公告)号：US2711464A

公开(公告)日：1955-06-21

申请号：US32311552

申请日：1952-11-28

Applicant: ELECTRONICS CORP AMERICA

Inventor： ANDERSON NORMAN C ,  SHAW BURTON E

IPC: H01L31/08

CPC classification number: H01L31/08 ,  Y10S257/912 ,  Y10T29/49107 ,  Y10T29/49169

公开(公告)号：US20140127835A1

公开(公告)日：2014-05-08

申请号：US14053750

申请日：2013-10-15

Applicant: Shanghai Huali Microelectronics Corporation

Inventor： Kai WANG ,  HungLin CHEN ,  Yin LONG ,  Qiliang NI ,  MingShen KUO

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L2924/0002 ,  Y10S257/911 ,  Y10S257/912 ,  H01L2924/00

Abstract: A method of detecting the circular uniformity of semiconductor circular contact holes. Several detection circuit structures are disposed on the semiconductor wafer: N-type active regions and P-type active regions; silicon dioxide layers separate the N-type active regions from the P-type active regions; the N-type active regions are formed in the P well and the P-type active regions are formed in the N well; polysilicon gates bridge the N-type active regions and the P-type active regions; gate oxide layers insulate the P-type regions and the N-type regions from the polysilicon gates, so that the P-type regions and the N-type regions are independent; the N-type active regions connect with circular contact holes while the P-type active regions and the polysilicon gates connect with oval contact holes; a electron beam scanner detects the circular uniformity of the contact holes. This invention advantageously reflects effectively and comprehensively the circular uniformity of the contact holes.

Abstract translation: 一种检测半导体圆形接触孔的圆形均匀性的方法。 多个检测电路结构设置在半导体晶片上：N型有源区和P型有源区; 二氧化硅层将N型有源区与P型有源区分开; 在P阱中形成N型有源区，在N阱中形成P型有源区; 多晶硅门桥接N型有源区和P型有源区; 栅极氧化层使P型区域和N型区域与多晶硅栅极绝缘，使得P型区域和N型区域是独立的; N型有源区域与圆形接触孔连接，而P型有源区域和多晶硅栅极与椭圆形接触孔连接; 电子束扫描器检测接触孔的圆形均匀性。 本发明有利地有效地反映了接触孔的圆形均匀性。

公开(公告)号：US07709367B2

公开(公告)日：2010-05-04

申请号：US11761577

申请日：2007-06-12

Applicant: Hae-Jung Lee ,  Ik-Soo Choi ,  Chang-Youn Hwang ,  Mi-Hyune You

Inventor： Hae-Jung Lee ,  Ik-Soo Choi ,  Chang-Youn Hwang ,  Mi-Hyune You

IPC: H01L21/44

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  Y10S257/906 ,  Y10S257/912

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract translation: 一种用于在半导体器件中制造存储节点接触的方法包括在衬底上形成着陆塞，在着陆塞上形成第一绝缘层，在第一绝缘层上形成位线图形，在该位上形成第二绝缘层 形成用于在所述第二绝缘层上形成存储节点接触的掩模图案，蚀刻所述第二绝缘层和所述第一绝缘层，直到所述着陆塞被暴露以形成包括具有圆形轮廓的部分的存储节点接触孔，填充导电 存储节点接触孔中的材料形成接触塞，并在接触插塞上形成存储节点。

公开(公告)号：US20080003811A1

公开(公告)日：2008-01-03

申请号：US11761577

申请日：2007-06-12

Applicant: Hae-Jung Lee ,  Ik-Soo Choi ,  Chang-Youn Hwang ,  Mi-Hyune You

Inventor： Hae-Jung Lee ,  Ik-Soo Choi ,  Chang-Youn Hwang ,  Mi-Hyune You

IPC: H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10855 ,  Y10S257/906 ,  Y10S257/912

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a landing plug over a substrate, forming a first insulation layer over the landing plug, forming a bit line pattern over the first insulation layer, forming a second insulation layer over the bit line pattern, forming a mask pattern for forming a storage node contact over the second insulation layer, etching the second and first insulation layers until the landing plug is exposed to form a storage node contact hole including a portion having a rounded profile, filling a conductive material in the storage node contact hole to form a contact plug, and forming a storage node over the contact plug.

Abstract translation: 一种用于在半导体器件中制造存储节点接触的方法包括在衬底上形成着陆塞，在着陆塞上形成第一绝缘层，在第一绝缘层上形成位线图形，在该位上形成第二绝缘层 形成用于在所述第二绝缘层上形成存储节点接触的掩模图案，蚀刻所述第二绝缘层和所述第一绝缘层，直到所述着陆塞被暴露以形成包括具有圆形轮廓的部分的存储节点接触孔，填充导电 存储节点接触孔中的材料形成接触塞，并在接触插塞上形成存储节点。

公开(公告)号：US20040119865A1

公开(公告)日：2004-06-24

申请号：US10688073

申请日：2003-10-17

Applicant: SANYO ELECTRIC CO., LTD.

Inventor： Yoshihiro Okada ,  Yuzo Otsuru

IPC: H04N003/14 ,  H04N005/335

CPC classification number: H01L27/14812 ,  Y10S257/912

Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.

Abstract translation: 一种固体摄像元件，包括多个垂直移位寄存器，每个垂直移位寄存器被布置为对应于矩阵排列中的多个光接收像素的列，设置在多个垂直移位寄存器的输出侧的水平移位寄存器，以及 输出部分设置在水平移位寄存器的输出侧。 在该固体摄像元件中，在一个导电半导体衬底的一个主表面上形成反向导电半导体区域，多个光接收像素，多个垂直移位寄存器，水平移位寄存器和输出部分形成在 半导体区域和形成有输出部分的半导体区域的一部分具有比形成水平移位寄存器的半导体区域的部分更高的掺杂剂浓度。