公开(公告)号：US07964462B2

公开(公告)日：2011-06-21

申请号：US12270033

申请日：2008-11-13

Applicant: Dong-chul Yoo ,  Han-mei Choi ,  Kwang-hee Lee ,  Kyong-won An ,  Cha-young Yoo

Inventor： Dong-chul Yoo ,  Han-mei Choi ,  Kwang-hee Lee ,  Kyong-won An ,  Cha-young Yoo

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/3115 ,  H01L21/3162 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括：在其上形成有栅极绝缘层的基板上形成电荷存储层; 使用包括金属氧化物层前体和第一氧化剂的第一反应源在电荷存储层上形成第一金属氧化物层，并且使用包括第二氧化剂的第二反应源将第一金属氧化物层改变为第二金属氧化物层 具有比第一氧化剂更大的氧化能力，并且重复形成第一金属氧化物层和将第一金属氧化物层改变为第二金属氧化物层数次以形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成电极层。

公开(公告)号：US20090124071A1

公开(公告)日：2009-05-14

申请号：US12270033

申请日：2008-11-13

Applicant: Dong-chul Yoo ,  Han-mei Choi ,  Kwang-hee Lee ,  Kyong-won An ,  Cha-young Yoo

Inventor： Dong-chul Yoo ,  Han-mei Choi ,  Kwang-hee Lee ,  Kyong-won An ,  Cha-young Yoo

IPC: H01L21/28 ,  H01L21/316

CPC classification number: H01L29/792 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/3115 ,  H01L21/3162 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes: forming a charge storage layer on a substrate on which a gate insulating layer is formed; forming a first metal oxide layer on the charge storage layer using a first reaction source including a metal oxide layer precursor and a first oxidizing agent and changing the first metal oxide layer to a second metal oxide layer using a second reaction source including a second oxidizing agent having larger oxidizing power than the first oxidizing agent and repeating the forming of the first metal oxide layer and the changing of the first metal oxide layer to the second metal oxide layer several times to form a blocking insulating layer; and forming an electrode layer on the blocking insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括：在其上形成有栅极绝缘层的基板上形成电荷存储层; 使用包括金属氧化物层前体和第一氧化剂的第一反应源在电荷存储层上形成第一金属氧化物层，并且使用包括第二氧化剂的第二反应源将第一金属氧化物层改变为第二金属氧化物层 具有比第一氧化剂更大的氧化能力，并且重复形成第一金属氧化物层和将第一金属氧化物层改变为第二金属氧化物层数次以形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成电极层。

公开(公告)号：US20090124070A1

公开(公告)日：2009-05-14

申请号：US12270014

申请日：2008-11-13

Applicant: Dong Chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

Inventor： Dong Chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

IPC: H01L21/3205

CPC classification number: H01L21/31616 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3145 ,  H01L21/31604

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Abstract translation: 提供了制造半导体器件的方法，包括在半导体衬底上的栅极绝缘层上形成电荷存储层。 在电荷存储层上形成阻挡绝缘层，在隔离绝缘层上形成电极层。 阻挡绝缘层可以通过在第一温度下形成下部金属氧化物层并在低于第一温度的第二温度下在下部金属氧化物层上形成上部金属氧化物层而形成。

公开(公告)号：US20160056169A1

公开(公告)日：2016-02-25

申请号：US14657663

申请日：2015-03-13

Applicant: Woong LEE ,  Chae Ho KIM ,  Kyong Won AN ,  Joon Suk LEE ,  Woo Sung LEE ,  Hun Hyeong LIM

Inventor： Woong LEE ,  Chae Ho KIM ,  Kyong Won AN ,  Joon Suk LEE ,  Woo Sung LEE ,  Hun Hyeong LIM

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/7926

Abstract: According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate.

Abstract translation: 根据示例性实施例，制造半导体器件的方法包括在衬底上交替层叠层间绝缘层和中间层，形成穿过层间绝缘层和中间层的开口，以在衬底中形成凹陷区域，形成第一外延层 凹陷区域中的凹陷表面，以及使用第一外延层作为晶种层形成第二外延层。 第二外延层填充凹陷区域并在衬底上方延伸。

公开(公告)号：US20140183749A1

公开(公告)日：2014-07-03

申请号：US14109159

申请日：2013-12-17

Applicant: SANGHOON LEE ,  HYUNYONG GO ,  SUNGGIL KIM ,  KYONG-WON AN ,  WOOSUNG LEE ,  YONGSEOK CHO

Inventor： SANGHOON LEE ,  HYUNYONG GO ,  SUNGGIL KIM ,  KYONG-WON AN ,  WOOSUNG LEE ,  YONGSEOK CHO

IPC: H01L23/528

CPC classification number: H01L27/10855 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.

Abstract translation: 在制造半导体器件的方法中，通过留下部分牺牲层来形成牺牲层图案，而不是完全去除牺牲层。 因此，可以提高半导体器件的可靠性，并且可以简化其制造工艺。

公开(公告)号：US09653472B2

公开(公告)日：2017-05-16

申请号：US14657663

申请日：2015-03-13

Applicant: Woong Lee ,  Chae Ho Kim ,  Kyong Won An ,  Joon Suk Lee ,  Woo Sung Lee ,  Hun Hyeong Lim

Inventor： Woong Lee ,  Chae Ho Kim ,  Kyong Won An ,  Joon Suk Lee ,  Woo Sung Lee ,  Hun Hyeong Lim

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11578 ,  H01L27/105 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/7926

Abstract: According to example embodiments, a method of fabricating a semiconductor device includes alternately stacking interlayer insulating layers and intermediate layers on a substrate, forming openings passing through the interlayer insulating layers and the intermediate layers to form recessed regions in the substrate, forming first epitaxial layers on recessed surfaces in the recessed regions, and forming second epitaxial layers using the first epitaxial layers as seed layers. The second epitaxial layers fill the recessed regions and extend above the substrate.

公开(公告)号：US20140084358A1

公开(公告)日：2014-03-27

申请号：US13969912

申请日：2013-08-19

Applicant: Woo-Sung LEE ,  Kyong-Won AN

Inventor： Woo-Sung LEE ,  Kyong-Won AN

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A nonvolatile memory device includes an insulating pattern extending in a first direction, a conductive pattern on the insulating pattern, and an electrode structure extending in the first direction. The electrode structure is adjacent the insulating pattern and conductive pattern, and includes an alternating pattern of gate electrodes and interlayer insulating films. A protection film adjacent a side surface of the electrode structure has a shorter length in the first direction than a length of the electrode structure.

Abstract translation: 非易失性存储器件包括沿第一方向延伸的绝缘图案，绝缘图案上的导电图案和沿第一方向延伸的电极结构。 电极结构与绝缘图案和导电图案相邻，并且包括栅电极和层间绝缘膜的交替图案。 与电极结构的侧表面相邻的保护膜在第一方向上比电极结构的长度具有更短的长度。

公开(公告)号：US07790591B2

公开(公告)日：2010-09-07

申请号：US12270014

申请日：2008-11-13

Applicant: Dong-chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

Inventor： Dong-chul Yoo ,  Myoung-bum Lee ,  Young-geun Park ,  Han-mei Choi ,  Se-hoon Oh ,  Byong-ju Kim ,  Kyong-won An ,  Seon-ho Jo

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/31616 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3145 ,  H01L21/31604

Abstract: Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Abstract translation: 提供了制造半导体器件的方法，包括在半导体衬底上的栅极绝缘层上形成电荷存储层。 在电荷存储层上形成阻挡绝缘层，在隔离绝缘层上形成电极层。 阻挡绝缘层可以通过在第一温度下形成下部金属氧化物层并在低于第一温度的第二温度下在下部金属氧化物层上形成上部金属氧化物层而形成。