公开(公告)号：US09018610B2

公开(公告)日：2015-04-28

申请号：US13483462

申请日：2012-05-30

Applicant: Nam Kyun Park ,  Kang Sik Choi

Inventor： Nam Kyun Park ,  Kang Sik Choi

IPC: H01L47/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/22 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/0688 ,  H01L27/101 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/147

Abstract: A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.

Abstract translation: 提供了能够提高集成密度的电阻式存储器件。 电阻式存储器件包括半导体衬底，多个电阻存储器单元，被配置为堆叠在半导体衬底上并彼此绝缘，其中多个电阻存储单元中的每一个包括开关晶体管和电阻器件层，电连接到 所述开关晶体管，电连接到所述多个堆叠的电阻性存储单元的公共源极线，以及电连接到所述多个堆叠的电阻性存储器单元并与所述公共源极线绝缘的位线。

公开(公告)号：US08796781B2

公开(公告)日：2014-08-05

申请号：US13598364

申请日：2012-08-29

Applicant: Jang Uk Lee ,  Sung Cheoul Kim ,  Kang Sik Choi ,  Suk Ki Kim

Inventor： Jang Uk Lee ,  Sung Cheoul Kim ,  Kang Sik Choi ,  Suk Ki Kim

IPC: H01L27/11

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

公开(公告)号：US20130153847A1

公开(公告)日：2013-06-20

申请号：US13483462

申请日：2012-05-30

Applicant: Nam Kyun PARK ,  Kang Sik Choi

Inventor： Nam Kyun PARK ,  Kang Sik Choi

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L27/0688 ,  H01L27/101 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/147

Abstract: A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line.

Abstract translation: 提供了能够提高集成密度的电阻式存储器件。 电阻式存储器件包括半导体衬底，多个电阻存储器单元，被配置为堆叠在半导体衬底上并彼此绝缘，其中多个电阻性存储单元中的每一个包括开关晶体管和电阻器件层，电连接到 所述开关晶体管，电连接到所述多个堆叠的电阻性存储单元的公共源极线，以及电连接到所述多个堆叠的电阻性存储器单元并与所述公共源极线绝缘的位线。

公开(公告)号：US20130014054A1

公开(公告)日：2013-01-10

申请号：US13404400

申请日：2012-02-24

Applicant: Kang-Sik CHOI ,  Jung-Woo CHOI ,  Gi-Yong LEE ,  Eun-Young PARK

Inventor： Kang-Sik CHOI ,  Jung-Woo CHOI ,  Gi-Yong LEE ,  Eun-Young PARK

IPC: G06F17/00

CPC classification number: G06F17/211 ,  G06F17/24

Abstract: A method and an apparatus for editing a text in a mobile terminal are provided. The method includes a copying step of changing a color of at least one text selected by a copy icon if the copy step is selected while displaying texts on a display, and storing the at least one color-changed text, and a pasting step of pasting a text selected from a list including at least one text stored in the copying step to a specific location on the display if the paste step is selected.

Abstract translation: 提供了一种用于在移动终端中编辑文本的方法和装置。 该方法包括如果在显示器上显示文本的同时选择复制步骤并且存储至少一个变色文本以及粘贴粘贴步骤的情况下，更改由复制图标选择的至少一个文本的颜色的复制步骤 如果选择了粘贴步骤，则从包括在复印步骤中存储的至少一个文本的列表中选择的文本到显示器上的特定位置。

公开(公告)号：US08252623B2

公开(公告)日：2012-08-28

申请号：US13402220

申请日：2012-02-22

Applicant: Jang Uk Lee ,  Kang Sik Choi

Inventor： Jang Uk Lee ,  Kang Sik Choi

IPC: H01L21/00

CPC classification number: H01L27/2409 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract translation: 提出了一种相变存储器件及其制造方法。 相变存储器件包括第一布线，第二布线，存储单元和导电触点。 第一布线基本上彼此平行地布置，使得第一布线被分组成奇数和偶数编号的第一布线。 存储单元耦合到第一和第二布线。 耦合到第一布线的导通触点使得只有一个导电触点耦合到相应的奇数编号的第一布线的中心。 也只有两个对应的导电触点耦合到对应的偶数第一布线的相对边缘。 因此，导通触点设置在第一布线上，使得导电触点相对于紧邻的第一布线彼此不相邻。

公开(公告)号：US20120187338A1

公开(公告)日：2012-07-26

申请号：US13499129

申请日：2010-09-03

Applicant: Chang Hae Kim ,  Hwa Sung You ,  Kang Sik Choi

Inventor： Chang Hae Kim ,  Hwa Sung You ,  Kang Sik Choi

IPC: C09K11/79

CPC classification number: C09K11/7792 ,  C09K11/7734 ,  H01L24/45 ,  H01L33/502 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed are a (halo)silicate-based phosphor and a manufacturing method of the same. More particularly, the disclosed phosphor is a novel (halo)silicate-based phosphor manufactured by using a (halo)silicate-based host material containing an alkaline earth metal, and europium as an activator.

Abstract translation: 公开了（卤）硅酸盐系荧光体及其制造方法。 更具体地说，所公开的荧光体是通过使用含有碱土金属的（卤代）硅酸盐主体材料和铕作为活化剂而制造的新型（卤代）硅酸盐基荧光体。

公开(公告)号：US20120149163A1

公开(公告)日：2012-06-14

申请号：US13402220

申请日：2012-02-22

Applicant: Jang Uk LEE ,  Kang Sik CHOI

Inventor： Jang Uk LEE ,  Kang Sik CHOI

IPC: H01L21/62

CPC classification number: H01L27/2409 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract translation: 提出了一种相变存储器件及其制造方法。 相变存储器件包括第一布线，第二布线，存储单元和导电触点。 第一布线基本上彼此平行地布置，使得第一布线被分组成奇数和偶数编号的第一布线。 存储单元耦合到第一和第二布线。 耦合到第一布线的导通触点使得只有一个导电触点耦合到相应的奇数编号的第一布线的中心。 也只有两个对应的导电触点耦合到对应的偶数第一布线的相对边缘。 因此，导通触点设置在第一布线上，使得导电触点相对于紧邻的第一布线彼此不相邻。

公开(公告)号：US20100301305A1

公开(公告)日：2010-12-02

申请号：US12641535

申请日：2009-12-18

Applicant: Jang Uk Lee ,  Kang Sik Choi

Inventor： Jang Uk Lee ,  Kang Sik Choi

IPC: H01L45/00 ,  H01L21/768 ,  H01L27/04

CPC classification number: H01L27/2409 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract translation: 提出了一种相变存储器件及其制造方法。 相变存储器件包括第一布线，第二布线，存储单元和导电触点。 第一布线基本上彼此平行地布置，使得第一布线被分组成奇数和偶数编号的第一布线。 存储单元耦合到第一和第二布线。 耦合到第一布线的导通触点使得只有一个导电触点耦合到相应的奇数编号的第一布线的中心。 也只有两个对应的导电触点耦合到对应的偶数第一布线的相对边缘。 因此，导通触点设置在第一布线上，使得导电触点相对于紧邻的第一布线彼此不相邻。

公开(公告)号：US07833861B2

公开(公告)日：2010-11-16

申请号：US11865646

申请日：2007-10-01

Applicant: Kang Sik Choi

Inventor： Kang Sik Choi

IPC: H01L21/336 ,  H01L21/762

CPC classification number: H01L29/045 ,  H01L29/1083 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/7846

Abstract: A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate.

Abstract translation: 具有凹陷沟道结构的半导体器件包括：半导体衬底，其具有形成在有源区域中的栅极形成区域中的凹部; 绝缘层，形成在所述半导体衬底中，以限定所述有源区并形成为在沟道宽度方向上施加拉伸应力; 形成在所述绝缘层的表面上并形成为在沟道高度方向施加压缩应力的应力器; 形成在活动区域​​的凹部上的门; 以及形成在栅极两侧的有源区域的表面中的源极/漏极区域。

公开(公告)号：US20070241420A1

公开(公告)日：2007-10-18

申请号：US11529381

申请日：2006-09-29

Applicant: Kang Sik Choi

Inventor： Kang Sik Choi

IPC: H01L29/00

CPC classification number: H01L29/785 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/115 ,  H01L29/42392 ,  H01L29/66795

Abstract: The semiconductor device includes a device isolation structure formed in a semiconductor substrate to define an active region, a bridge type channel structure formed in the active region, and a coaxial type gate electrode surrounding the bridge type channel structure of a gate region. The bridge type channel structure is separated from the semiconductor substrate thereunder by a predetermined distance in a vertical direction.

Abstract translation: 半导体器件包括形成在半导体衬底中以限定有源区的器件隔离结构，在有源区中形成的桥型沟道结构，以及围绕栅极区的桥型沟道结构的同轴型栅电极。 桥式沟道结构在其下方的半导体衬底沿垂直方向与预定距离分开。