公开(公告)号：US20130241000A1

公开(公告)日：2013-09-19

申请号：US13598364

申请日：2012-08-29

Applicant: Jang Uk LEE ,  Sung Cheoul Kim ,  Kang Sik Choi ,  Suk ki Kim

Inventor： Jang Uk LEE ,  Sung Cheoul Kim ,  Kang Sik Choi ,  Suk ki Kim

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/11

CPC classification number: H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: A semiconductor memory device includes a semiconductor substrate, an active region including a plurality of unit active regions and disposed over and spaced from the semiconductor substrate, a pair of word lines formed on a top surface and sides of the unit active region, a dummy word line disposed at a contact of the unit active regions and formed on top surfaces and sides of the unit active regions, a source region in the unit active region between the pair of word lines and electrically connected to the semiconductor substrate, drain regions formed in the unit active region between the pair of word lines and the dummy word line, and first storage layers formed on the drain regions and electrically connected to the drain regions.

Abstract translation: 半导体存储器件包括半导体衬底，包括多个单元有源区并且设置在半导体衬底之上并与其隔开的有源区，形成在单位有效区的顶表面和侧面上的一对字线，虚拟字 设置在单元有源区的接触处并形成在单元有源区的顶表面和侧面上的线，在该对字线之间的单元有源区中的源极区，并且电连接到半导体衬底，形成在该半导体衬底中的漏极区 在一对字线和伪字线之间的单位有效区域，以及形成在漏极区域上并电连接到漏极区域的第一存储层。

公开(公告)号：US20110143477A1

公开(公告)日：2011-06-16

申请号：US12834141

申请日：2010-07-12

Applicant: Jang Uk LEE ,  Kang Sik CHOI ,  Hae Chan PARK ,  Jin Hyock KIM ,  Ja Chun KU

Inventor： Jang Uk LEE ,  Kang Sik CHOI ,  Hae Chan PARK ,  Jin Hyock KIM ,  Ja Chun KU

IPC: H01L21/28

CPC classification number: H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

Abstract: A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns.

Abstract translation: 提供一种制造相变存储器件的方法。 在半导体衬底上形成具有以恒定距离隔开的多个金属字线的第一绝缘层。 形成具有阻挡金属层，多晶硅层和硬掩模层的多个线结构以覆盖在多个金属字线上。 在线路结构之间形成第二绝缘层。 通过使用与金属字线交叉的掩模图案蚀刻线结构的硬掩模层和多晶硅层来形成交叉图案。 第三绝缘层埋在交叉图案之间的空间内。 形成自对准的相变接触孔，同时，通过选择性地去除构成交叉图案的硬掩模层，形成由剩余多晶硅层形成的二极管图案。

公开(公告)号：US20120149163A1

公开(公告)日：2012-06-14

申请号：US13402220

申请日：2012-02-22

Applicant: Jang Uk LEE ,  Kang Sik CHOI

Inventor： Jang Uk LEE ,  Kang Sik CHOI

IPC: H01L21/62

CPC classification number: H01L27/2409 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract translation: 提出了一种相变存储器件及其制造方法。 相变存储器件包括第一布线，第二布线，存储单元和导电触点。 第一布线基本上彼此平行地布置，使得第一布线被分组成奇数和偶数编号的第一布线。 存储单元耦合到第一和第二布线。 耦合到第一布线的导通触点使得只有一个导电触点耦合到相应的奇数编号的第一布线的中心。 也只有两个对应的导电触点耦合到对应的偶数第一布线的相对边缘。 因此，导通触点设置在第一布线上，使得导电触点相对于紧邻的第一布线彼此不相邻。

公开(公告)号：US20130099386A1

公开(公告)日：2013-04-25

申请号：US13598303

申请日：2012-08-29

Applicant: Jang Uk LEE

Inventor： Jang Uk LEE

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L45/1253 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

Abstract: A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area.

Abstract translation: 提供一种具有形成在互连上并能够降低互连电阻的单元图形的半导体存储器件及其制造方法。 半导体器件包括其中限定了单元区域，核心区域和外围区域并形成底部结构的半导体基板，形成在半导体基板的整个结构上的导电线，形成在该半导体基板上的存储单元图案 电池区域中的导线，以及形成在芯区域和外围区域中的导电线中的任一个上的虚设导电图案。

公开(公告)号：US20100327249A1

公开(公告)日：2010-12-30

申请号：US12635950

申请日：2009-12-11

Applicant: Mi Ra CHOI ,  Jang Uk LEE

Inventor： Mi Ra CHOI ,  Jang Uk LEE

IPC: H01L45/00 ,  H01L29/18 ,  H01L21/06

CPC classification number: H01L27/0207 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/7833 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

Abstract translation: 提出了具有改进的字线电阻的相变存储器件及其制造方法。 相变存储器件包括半导体衬底，字线，层间绝缘膜，捆扎线，多个电流路径，开关元件和相变可变电阻器。 字线形成在半导体衬底的单元区域中。 形成在字线上的层间绝缘膜。 捆扎线形成在层间绝缘膜上，使得捆扎线与字线的顶部重叠。 电流路径将字线与捆扎线电连接在一起。 开关元件电连接到捆扎线。 相变可变电阻器电连接到开关元件。

公开(公告)号：US20120326112A1

公开(公告)日：2012-12-27

申请号：US13331448

申请日：2011-12-20

Applicant: Jang Uk LEE

Inventor： Jang Uk LEE

IPC: H01L47/00 ,  H01L21/02

CPC classification number: H01L45/1233 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144

Abstract: A phase-change random access memory (PCRAM) device and a method of manufacturing the same are provided. The PCRAM device includes a semiconductor substrate, a junction word line formed on the semiconductor substrate, an epitaxial word line formed on the junction word line, and a switching device formed on the epitaxial word line.

Abstract translation: 提供了相变随机存取存储器（PCRAM）装置及其制造方法。 PCRAM装置包括半导体衬底，形成在半导体衬底上的结字线，形成在结字线上的外延字线以及形成在外延字线上的开关器件。

公开(公告)号：US20110147689A1

公开(公告)日：2011-06-23

申请号：US12782839

申请日：2010-05-19

Applicant: Jang Uk LEE

Inventor： Jang Uk LEE

IPC: H01L45/00 ,  H01L21/06

CPC classification number: H01L28/20 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory device capable of reducing disturbances between adjacent PRAM memory cells and a fabrication method are presented. The phase change memory device includes word lines, heating electrodes, an interlayer insulating layer, and a phase change lines. The word lines are formed on a semiconductor substrate and extend in parallel with a constant space. The heating electrodes are electrically connected to the plurality of word lines. The interlayer insulating layer insulates the heating electrodes. The phase change lines extend in a direction orthogonal to the word line and are electrically connected to the heating electrodes. Curves are formed on a surface of the interlayer insulating layer between the word lines such that the effective length of the phase change layer between adjacent heating electrodes is larger than the physical distance between the adjacent heating electrodes.

Abstract translation: 提出了能够减少相邻PRAM存储单元之间的干扰的相变存储器件和制造方法。 相变存储器件包括字线，加热电极，层间绝缘层和相变线。 字线形成在半导体衬底上并且以恒定的空间平行延伸。 加热电极与多条字线电连接。 层间绝缘层绝热加热电极。 相变线在与字线正交的方向上延伸并且电连接到加热电极。 在字线之间的层间绝缘层的表面上形成曲线，使得相邻加热电极之间的相变层的有效长度大于相邻加热电极之间的物理距离。

公开(公告)号：US20120329222A1

公开(公告)日：2012-12-27

申请号：US13605167

申请日：2012-09-06

Applicant: Mi Ra CHOI ,  Jang Uk LEE

Inventor： Mi Ra CHOI ,  Jang Uk LEE

IPC: H01L21/8239

CPC classification number: H01L27/0207 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/7833 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

Abstract translation: 提出了具有改进的字线电阻的相变存储器件及其制造方法。 相变存储器件包括半导体衬底，字线，层间绝缘膜，捆扎线，多个电流路径，开关元件和相变可变电阻器。 字线形成在半导体衬底的单元区域中。 形成在字线上的层间绝缘膜。 捆扎线形成在层间绝缘膜上，使得捆扎线与字线的顶部重叠。 电流路径将字线与捆扎线电连接在一起。 开关元件电连接到捆扎线。 相变可变电阻器电连接到开关元件。

公开(公告)号：US20100327252A1

公开(公告)日：2010-12-30

申请号：US12647600

申请日：2009-12-28

Applicant: Jang Uk LEE

Inventor： Jang Uk LEE

IPC: H01L45/00 ,  H01L21/20 ,  H01L21/28 ,  H01L29/00

CPC classification number: H01L45/16 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

Abstract: A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract translation: 提供一种相变存储装置，其包括具有形成在半导体衬底的有源区上的沟槽的棒状的第一电极，形成在沟槽的底部的第二电极和形成在第二沟道的底部的底部电极触点 电极。