公开(公告)号：US20090068823A1

公开(公告)日：2009-03-12

申请号：US12145914

申请日：2008-06-25

申请人： Soo Jin Hong ,  Si-Young Choi ,  Tai-Su Park ,  Jin-Wook Lee ,  Jong-Hoon Kang ,  Mi-Jin Kim

发明人： Soo Jin Hong ,  Si-Young Choi ,  Tai-Su Park ,  Jin-Wook Lee ,  Jong-Hoon Kang ,  Mi-Jin Kim

IPC分类号： H01L21/02 ,  H01J37/08

CPC分类号： H01L21/2236 ,  H01J37/32412 ,  H01J37/32449

摘要： In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.

摘要翻译： 在等离子体离子掺杂操作中，将晶片定位在反应室内的基座上，并且将离子掺杂源气体在晶片的主表面上方的反应室上部进行等离子化，同时将控制气体供应到反应室中 反应室的下部与晶片的主表面相对，从而将离子掺杂到晶片的主表面。 离子掺杂源气体可以包括至少一种卤化物气体，并且控制气体可以包括至少一种沉积气体，例如硅烷气体。 在另外的实施方案中，可以向反应室供应诸如惰性气体的稀释气体，同时供应离子掺杂源气体和控制气体。 描述了相关的等离子体离子掺杂装置。

公开(公告)号：US20130205856A1

公开(公告)日：2013-08-15

申请号：US13418578

申请日：2012-03-13

申请人： Jong-hoon Kang ,  Hyun-jun Kim ,  Hong-il Jo ,  Young-myung Kim

发明人： Jong-hoon Kang ,  Hyun-jun Kim ,  Hong-il Jo ,  Young-myung Kim

IPC分类号： B21B19/14 ,  B21B37/78

CPC分类号： B21H1/06

摘要： Disclosed herein is an apparatus and method for forming a product having an asymmetric cross-section using a ring rolling process. The method of forming a product having an asymmetric cross-section uses a ring rolling process that uses a ring rolling apparatus, the ring rolling apparatus comprising: a main roll pressing a circumferential outer surface of a blank, a pressure roll pressing a circumferential inner surface of the blank, and a pair of axial rolls pressing upper and lower surfaces of the blank, wherein a protrusion provided on the pressure roll comes into contact with a depressed portion formed on the circumferential inner surface of the blank, and as a width of the blank varies, the pressure roll moves in a vertical direction.

摘要翻译： 本文公开了一种使用环轧工艺形成具有不对称横截面的产品的装置和方法。 形成具有不对称横截面的产品的方法使用使用环轧设备的环轧工艺，所述环轧设备包括：主辊压制坯料的周向外表面，压辊压制周向内表面 以及一对按压坯料的上表面和下表面的轴向辊，其中设置在压力辊上的突起与形成在坯料的周向内表面上的凹陷部分接触，并且作为 空白变化，压力辊在垂直方向上移动。

公开(公告)号：US20120282769A1

公开(公告)日：2012-11-08

申请号：US13551251

申请日：2012-07-17

申请人： Jeong-Do Ryu ,  Si-Young CHOI ,  Yu-Gyun SHIN ,  Tai-Su PARK ,  Dong-Chan KIM ,  Jong-Ryeol YOO ,  Seong-Hoon JEONG ,  Jong-Hoon KANG

发明人： Jeong-Do Ryu ,  Si-Young CHOI ,  Yu-Gyun SHIN ,  Tai-Su PARK ,  Dong-Chan KIM ,  Jong-Ryeol YOO ,  Seong-Hoon JEONG ,  Jong-Hoon KANG

IPC分类号： H01L21/28

CPC分类号： H01L21/28061 ,  H01L21/28247 ,  H01L21/3211 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1104

摘要： Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

摘要翻译： 形成集成电路器件的方法包括在衬底上形成含硅的导电层，并在导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，选择性地蚀刻导电层以限定其上的第一侧壁。 可以将导电层的第一侧壁暴露于氮等离子体，从而在第一侧壁上形成第一氮化硅层。 然后再次选择性地蚀刻导电层以暴露其上没有第一氮化硅层的第二侧壁。 在选择性蚀刻导电层的第二步骤期间，掩模图案可以再次用作蚀刻掩模。

公开(公告)号：US20120269498A1

公开(公告)日：2012-10-25

申请号：US13452052

申请日：2012-04-20

申请人： Gonsu KANG ,  Sangbom KANG ,  Jaeyoung PARK ,  Sungho KANG ,  Taegon KIM ,  Hyunsub EARM ,  Jong-hoon KANG ,  Kang Hun MOON ,  Han Ki LEE

发明人： Gonsu KANG ,  Sangbom KANG ,  Jaeyoung PARK ,  Sungho KANG ,  Taegon KIM ,  Hyunsub EARM ,  Jong-hoon KANG ,  Kang Hun MOON ,  Han Ki LEE

IPC分类号： F27D5/00 ,  F26B3/30

CPC分类号： F27B17/0025 ,  H01L21/67115 ,  H01L21/6875

摘要： A substrate treatment apparatus and a supporting unit are provided. The substrate treatment apparatus includes a chamber in which a substrate is processed; a supporting unit that is disposed in the chamber and is configured to support the substrate; and a heating member that is configured to apply heat to the substrate supported by the supporting unit. The supporting unit includes a plate; a plurality of supporting pins upwardly protruding from the plate; and at least one auxiliary pin upwardly protruding from the plate. A distance between a central point of the plate and the at least one auxiliary pin is different from a distance between the central point of the plate and the supporting pins.

摘要翻译： 提供了基板处理装置和支撑单元。 基板处理装置包括：处理基板的室; 支撑单元，其设置在所述室中并且构造成支撑所述基板; 以及加热构件，其构造成对由所述支撑单元支撑的所述基板施加热量。 支撑单元包括板; 从所述板向上突出的多个支撑销; 以及从板向上突出的至少一个辅助销。 板的中心点和至少一个辅助销之间的距离不同于板的中心点和支撑销之间的距离。

公开(公告)号：US20100072545A1

公开(公告)日：2010-03-25

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹陷。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US20080035170A1

公开(公告)日：2008-02-14

申请号：US11878493

申请日：2007-07-25

申请人： Kye-Hyun Baek ,  Jong-Hoon Kang ,  Yong-Jin Kim ,  Young-Soo Lim

发明人： Kye-Hyun Baek ,  Jong-Hoon Kang ,  Yong-Jin Kim ,  Young-Soo Lim

IPC分类号： B08B6/00

CPC分类号： B08B7/0035 ,  H01J37/32862

摘要： In a cleaning apparatus and a method of cleaning a chamber used in manufacturing a semiconductor device, a first plasma may be provided into a chamber to remove a first residue from an inner wall of the chamber where the first residue is attached. A second plasma may then be provided into the chamber to remove a second residue formed by the first plasma from an inside of the chamber where the second residue remains. The second residue formed by the first plasma used to clean the chamber may not pollute a semiconductor substrate located in the chamber.

摘要翻译： 在清洁装置和清洁用于制造半导体装置的室的方法中，可以将第一等离子体提供到室中，以从第一残留物附着的室的内壁去除第一残留物。 然后可以将第二等离子体提供到腔室中以从残留有第二残留物的腔室的内部除去由第一等离子体形成的第二残留物。 由用于清洁腔室的第一等离子体形成的第二残留物可能不会污染位于腔室中的半导体衬底。

公开(公告)号：US09240357B2

公开(公告)日：2016-01-19

申请号：US14100651

申请日：2013-12-09

申请人： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

发明人： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

IPC分类号： H01L21/66 ,  H01L21/265 ,  H01L21/311 ,  H01L27/115

CPC分类号： H01L22/12 ,  H01L21/31116 ,  H01L22/20 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

摘要翻译： 根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。 扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

公开(公告)号：US09190495B2

公开(公告)日：2015-11-17

申请号：US12563473

申请日：2009-09-21

申请人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

发明人： Jeong-Do Ryu ,  Dong-Chan Kim ,  Seong-Hoon Jeong ,  Si-Young Choi ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jong-Ryeol Yoo ,  Jong-Hoon Kang

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423 ,  H01L29/51 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66795 ,  H01L21/28211 ,  H01L21/823412 ,  H01L27/105 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/66621 ,  H01L29/7851

摘要： A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

摘要翻译： 凹陷通道阵列晶体管可以包括衬底，栅极氧化物层，栅极电极和源极/漏极区域。 衬底可以具有有源区和隔离区。 可以在活性区域中形成凹部。 栅极氧化物层可以形成在凹部和基板上。 栅极氧化物层可以包括在凹部的侧端和有源区的侧壁与凹部的侧表面上的第二部分之间的交叉处的第一部分。 第一部分可以包括大于第二部分厚度的约70％的厚度。 栅极电极可以形成在栅极氧化物层上。 源极/漏极区域可以形成在衬底中。 因此，凹陷通道阵列晶体管可能具有减小的漏电流和增加的导通电流。

公开(公告)号：US08800336B2

公开(公告)日：2014-08-12

申请号：US13418578

申请日：2012-03-13

申请人： Jong-hoon Kang ,  Hyun-jun Kim ,  Hong-il Jo ,  Young-myung Kim

发明人： Jong-hoon Kang ,  Hyun-jun Kim ,  Hong-il Jo ,  Young-myung Kim

IPC分类号： B21D22/00 ,  B21D22/16

CPC分类号： B21H1/06

摘要： Disclosed herein is an apparatus and method for forming a product having an asymmetric cross-section using a ring rolling process. The method of forming a product having an asymmetric cross-section uses a ring rolling process that uses a ring rolling apparatus, the ring rolling apparatus comprising: a main roll pressing a circumferential outer surface of a blank, a pressure roll pressing a circumferential inner surface of the blank, and a pair of axial rolls pressing upper and lower surfaces of the blank, wherein a protrusion provided on the pressure roll comes into contact with a depressed portion formed on the circumferential inner surface of the blank, and as a width of the blank varies, the pressure roll moves in a vertical direction.

摘要翻译： 本文公开了一种使用环轧工艺形成具有不对称横截面的产品的装置和方法。 形成具有不对称横截面的产品的方法使用使用环轧设备的环轧工艺，所述环轧设备包括：主辊压制坯料的周向外表面，压辊压制周向内表面 以及一对按压坯料的上表面和下表面的轴向辊，其中设置在压力辊上的突起与形成在坯料的周向内表面上的凹陷部分接触，并且作为 空白变化，压力辊在垂直方向上移动。

公开(公告)号：US08492251B2

公开(公告)日：2013-07-23

申请号：US13596339

申请日：2012-08-28

申请人： Jong-Hoon Kang ,  Bong-Jin Kuh ,  Tae-Gon Kim ,  Han-Mei Choi ,  Ki-Chul Kim ,  Eun-Young Jo

发明人： Jong-Hoon Kang ,  Bong-Jin Kuh ,  Tae-Gon Kim ,  Han-Mei Choi ,  Ki-Chul Kim ,  Eun-Young Jo

IPC分类号： H01L21/20

CPC分类号： H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/268 ,  H01L21/324 ,  H01L29/045

摘要： A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.

摘要翻译： 薄层结构包括衬底，暴露衬底的上表面的一部分的阻挡图案以及在衬底的上表面部分上的单晶半导体层，其中所述衬底的所有外表面 单晶半导体层具有<100>晶体取向。 薄层结构由SEG工艺形成，其中控制温度以防止原子沿着朝向衬底上表面的中心部分的方向迁移。 因此，该层的侧壁表面将不由小平面构成。