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    Memory cell with resistance-switching layers
    1.
    发明授权
    Memory cell with resistance-switching layers 有权
    具有电阻切换层的存储单元

    公开(公告)号：US08737111B2

    公开(公告)日：2014-05-27

    申请号：US13157191

    申请日：2011-06-09

    Applicant: Franz Kreupl ,  Xiying Costa ,  James Kai ,  Raghuveer S. Makala

    Inventor： Franz Kreupl ,  Xiying Costa ,  James Kai ,  Raghuveer S. Makala

    IPC: G11C11/00

    CPC classification number: H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

    Abstract: A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

    Abstract translation: 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。 离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

    STACKED METAL FIN CELL
    5.
    发明申请
    STACKED METAL FIN CELL 有权
    堆积金属细胞

    公开(公告)号：US20120153376A1

    公开(公告)日：2012-06-21

    申请号：US12974235

    申请日：2010-12-21

    Applicant: Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

    Inventor： Johann Alsmeier ,  Vinod Purayath ,  James Kai ,  George Matamis

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates located over the channel and a plurality of electrically conducting fins. Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates. Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.

    Abstract translation: 一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极和多个导电鳍片。 多个导电翅片中的每一个位于多个浮动栅极之一上。 多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极。 多个控制栅极中的每一个位于与多个浮动栅极和多个导电散热片中的每一个相邻的位置。

    Damascene method of making a nonvolatile memory device
    6.
    发明授权
    Damascene method of making a nonvolatile memory device 有权

    公开(公告)号：US08097498B2

    公开(公告)日：2012-01-17

    申请号：US12693322

    申请日：2010-01-25

    Applicant: Vinod Robert Purayath ,  George Matamis ,  James Kai ,  Takashi Orimoto

    Inventor： Vinod Robert Purayath ,  George Matamis ,  James Kai ,  Takashi Orimoto

    IPC: H01L21/20

    CPC classification number: H01L27/101 ,  H01L27/1021

    Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

    NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF
    8.
    发明申请
    NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF 审中-公开
    含有纳米级的非挥发性记忆体及其制备方法

    公开(公告)号：US20110186799A1

    公开(公告)日：2011-08-04

    申请号：US13020054

    申请日：2011-02-03

    Applicant: James Kai ,  Henry Chien ,  George Matamis

    Inventor： James Kai ,  Henry Chien ,  George Matamis

    IPC: H01L29/04 ,  H01L21/16 ,  H01L23/52 ,  B82Y99/00

    CPC classification number: B82Y10/00 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/149

    Abstract: A non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete conductive nano-features separated from each other by an insulating matrix, where the plurality of discrete nano-features are located in direct contact with the storage element, and a second electrode. An alternative non-volatile memory cell includes a first electrode, a steering element, a storage element located in series with the steering element, a plurality of discrete insulating nano-features separated from each other by a conductive matrix, where the plurality of discrete insulating nano-features are located in direct contact with the storage element, and a second electrode.

    Abstract translation: 非易失性存储单元包括第一电极，操舵元件，与转向元件串联定位的存储元件，多个离散的导电纳米特征，通过绝缘矩阵彼此分离，其中多个离散的纳米 - 特征位于与存储元件直接接触的位置，以及第二电极。 替代的非易失性存储单元包括第一电极，转向元件，与转向元件串联的存储元件，多个分立的绝缘纳米特征，其通过导电矩阵彼此分离，其中多个分立的绝缘 纳米特征位于与存储元件直接接触的位置，以及第二电极。

    Non-volatile memory with sidewall channels and raised source/drain regions
    9.
    发明授权
    Non-volatile memory with sidewall channels and raised source/drain regions 有权
    具有侧壁通道和升高的源极/漏极区域的非易失性存储器

    公开(公告)号：US07915664B2

    公开(公告)日：2011-03-29

    申请号：US12105242

    申请日：2008-04-17

    Applicant: Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    Inventor： Henry Chien ,  Takashi Orimoto ,  George Matamis ,  James Kai ,  Vinod R. Purayath

    IPC: H01L29/788

    CPC classification number: G11C8/10 ,  G11C8/04 ,  G11C11/5621 ,  G11C16/0483 ,  G11C19/00 ,  H01L21/28273 ,  H01L27/11521

    Abstract: A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.

    Abstract translation: 一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。 在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。 浮动门可以具有均匀的宽度或倒T形。 凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为 减少 侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

    Lithographically space-defined charge storage regions in non-volatile memory
    10.
    发明授权
    Lithographically space-defined charge storage regions in non-volatile memory 有权
    非易失性存储器中的光刻空间定义电荷存储区域

    公开(公告)号：US07807529B2

    公开(公告)日：2010-10-05

    申请号：US11960513

    申请日：2007-12-19

    Applicant: Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

    Inventor： Vinod Robert Purayath ,  George Matamis ,  Takashi Orimoto ,  James Kai

    IPC: H01L21/336

    CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

    Abstract: Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.

    Abstract translation: 在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。 牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。 用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。 可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。 较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。 存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域 的第一电荷存储区域。

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