公开(公告)号：US09117654B2

公开(公告)日：2015-08-25

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L21/467 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L23/544 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US08901746B2

公开(公告)日：2014-12-02

申请号：US14227625

申请日：2014-03-27

Applicant: Jang-ho Park ,  Jae-kwan Park ,  Dong-hwa Kwak ,  So-wi Jin ,  Byung-jun Hwang ,  Nam-su Lim

Inventor： Jang-ho Park ,  Jae-kwan Park ,  Dong-hwa Kwak ,  So-wi Jin ,  Byung-jun Hwang ,  Nam-su Lim

IPC: H01L23/48 ,  G11C5/06 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L23/48 ,  G11C5/063 ,  G11C16/0483 ,  H01L21/02697 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction.

Abstract translation: NAND闪速存储器件包括布置在多层衬底的公共层上的多个连续导体，所述多个连续导体包括沿着第一方向平行延伸的相应的导线，设置在相应导电线的端部处的相应接触焊盘和 相应的导电虚拟线沿着第二方向从接触焊盘平行延伸。

公开(公告)号：US08891297B2

公开(公告)日：2014-11-18

申请号：US13286301

申请日：2011-11-01

Applicant: Kalyan C. Kavalipurapu ,  Jae-Kwan Park

Inventor： Kalyan C. Kavalipurapu ,  Jae-Kwan Park

IPC: G11C7/00 ,  G11C16/28 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/28

Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first cell coupled to a first data line in response to a request to sense a data state of a second cell coupled to a second data line, applying a reference voltage to the first data line, floating the second data line while adjusting a voltage of the first data line to an adjusted voltage associated with the determined data state of the first cell, determining an effect on the second data line due, at least in part, to the adjusting the voltage of the first data line, and sensing the data state of the second cell by applying a particular sensing voltage to a selected access line to which the first cell and the second cell are coupled, the particular sensing voltage based on the determined effect on the second data line.

Abstract translation: 本公开涉及存储器单元感测。 一种或多种方法包括响应于感测耦合到第二数据线的第二单元的数据状态的请求来确定耦合到第一数据线的第一单元的数据状态，将参考电压施加到第一数据线， 在将第一数据线的电压调节到与所确定的第一单元的数据状态相关联的调整电压的同时，浮动第二数据线，确定对第二数据线的影响，至少部分地调整第二数据线的电压 并且通过将特定感测电压施加到第一单元和第二单元耦合到的所选择的接入线来感测第二单元的数据状态，基于所确定的对第二数据的影响的特定感测电压 线。

公开(公告)号：US20120252185A1

公开(公告)日：2012-10-04

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

Inventor： Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

IPC: H01L21/762 ,  H01L21/302 ,  H01L21/28

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US08178442B2

公开(公告)日：2012-05-15

申请号：US12501515

申请日：2009-07-13

Applicant: Sang-yong Park ,  Jae-kwan Park ,  Dong-hwa Kwak ,  Byung-kwan You

Inventor： Sang-yong Park ,  Jae-kwan Park ,  Dong-hwa Kwak ,  Byung-kwan You

IPC: H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11548

Abstract: A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively.

Abstract translation: 制造半导体器件的方法同时在器件的同一层上形成不同的图案。 该装置具有第一区域和第二区域。 在第二区域上形成有至少一个相对较宽的地形特征的低密度掩模图案，在第一区域上形成多个相对窄的地形特征，第一间隔物形成在第一区域中的窄形地貌特征的侧壁上 去除相对窄的地形特征，并且分别在第一和第二区域中同时转录第一间隔物的图案和相对宽的地形特征。

公开(公告)号：US08114778B2

公开(公告)日：2012-02-14

申请号：US12905318

申请日：2010-10-15

Applicant: Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

Inventor： Sang-yong Park ,  Jae-kwan Park ,  Yong-sik Yim ,  Jae-hwang Sim

IPC: H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.

Abstract translation: 更具体地，涉及一种在半导体器件中形成微小图案的方法，更具体地，涉及通过双重图案形成在基底图案之间具有偶数个插入图案的半导体器件中的微小图案的方法，包括在第一基本图案和第二基底图案之间的插入图案 在半导体基板上横向分离的图案，其中交替地重复第一插入图案和第二插入图案以形成插入图案，该方法包括对与第二插入图案相邻的第二插入图案进行部分蚀刻的操作 第二基本图案或形成屏蔽层图案的操作，从而形成偶数个插入图案。

公开(公告)号：US08057692B2

公开(公告)日：2011-11-15

申请号：US12290420

申请日：2008-10-30

Applicant: Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。

公开(公告)号：US07723775B2

公开(公告)日：2010-05-25

申请号：US12314192

申请日：2008-12-05

Applicant: Byung-jun Hwang ,  Jae-kwan Park ,  Jee-hoon Han ,  So-wi Jin ,  Nam-su Lim

Inventor： Byung-jun Hwang ,  Jae-kwan Park ,  Jee-hoon Han ,  So-wi Jin ,  Nam-su Lim

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.

Abstract translation: NAND闪速存储器件包括在衬底上沿第一方向延伸的多个有源区，所述有源区包括第一导电的第一阱，在与第一阱垂直的第二方向上在第一阱上延伸的多个字线 方向，第一和第二虚拟字线在第一阱上沿第二方向延伸，第一和第二虚拟字线彼此分离以限定它们之间的中间区域，第一和第二虚拟字线适于接收基本上 约0V的恒定偏置电压，以及在第一和第二伪字线之间的中间区域中的有源区域中的至少一个触点。

公开(公告)号：US20090236651A1

公开(公告)日：2009-09-24

申请号：US12463545

申请日：2009-05-11

Applicant: Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

Inventor： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC: H01L27/105 ,  H01L29/788

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

Abstract translation: 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US20090184697A1

公开(公告)日：2009-07-23

申请号：US12018442

申请日：2008-01-23

Applicant: Jae Kwan Park

Inventor： Jae Kwan Park

IPC: G05F1/62

CPC classification number: H02M3/073 ,  H02M2001/0025

Abstract: Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current mirroring digital-to-analog voltage regulator. The voltage regulator operates by mirroring a reference current onto a selectable current level and controlling the selectable current level with a digital input to a plurality of switched CMOS devices connected in parallel. The switched CMOS devices generate the selectable current level responsive to the digital input and proportional to the reference current. The selectable current level is combined with an output of a voltage divider to generate a monitor signal. The monitor signal is compared to a reference voltage and the results of the comparison controls a charge pump to generate a pumped voltage. The pumped voltage is fed back to the voltage divider, which includes a feedback resistor and a reference resistor connected in series between the pumped voltage and ground.

Abstract translation: 公开了用于使用电流镜像数模转换电压调节器来产生，调节和修改半导体器件上的各种电压电平的装置，系统和方法。 电压调节器通过将参考电流镜像到可选择的电平水平上并通过数字输入到并联连接的多个开关CMOS器件来控制可选择的电流电平来进行工作。 开关CMOS器件响应于数字输入并与参考电流成比例地产生可选择的电流电平。 可选择的电流电平与分压器的输出组合以产生监视信号。 将监视信号与参考电压进行比较，并且比较结果控制电荷泵以产生泵浦电压。 泵浦电压被反馈到分压器，分压器包括反馈电阻器和串联连接在泵浦电压和地之间的参考电阻器。