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6 条记录 (耗时 0.011 秒)

    On-chip capacitor
    3.
    发明授权
    On-chip capacitor 失效
    片上电容

    公开(公告)号：US06541840B1

    公开(公告)日：2003-04-01

    申请号：US09480456

    申请日：2000-01-11

    申请人： Fumihiko Terayama ,  Seiiti Yamazaki ,  Sintaro Mori

    发明人： Fumihiko Terayama ,  Seiiti Yamazaki ,  Sintaro Mori

    IPC分类号： H01L2900

    CPC分类号： H01L29/92

    摘要： An on-chip capacitor is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance is formed between a power source voltage and a grounding voltage formed between said first P-well region and said bottom N-well region. Thus it is not necessary to maintain a device region, to form a capacitance, to form wiring or maintain a wiring region as in a conventional MOS capacitance while it is possible to obtain a required decoupling capacitance.

    摘要翻译： 片上电容器设置有P型硅衬底，形成在所述P型硅衬底上的底部N阱区域，彼此相邻的第一P阱和形成在所述底部N阱区域上的第一N阱区域 形成在所述第一N阱区上的第一电极和形成在所述第一P阱区上的第二电极，形成有所述第一N阱区和所述第一P阱区并且形成电容的耦合表面 在所述第一P阱区域和所述底部N阱区域之间形成的电源电压和接地电压之间。 因此，不需要象现有的MOS电容那样保持器件区域，形成电容以形成布线或维持布线区域，同时可以获得所需的去耦电容。

    Semiconductor device and test method for connection between semiconductor devices
    4.
    发明授权
    Semiconductor device and test method for connection between semiconductor devices 失效
    用于半导体器件之间的连接的半导体器件和测试方法

    公开(公告)号：US5736849A

    公开(公告)日：1998-04-07

    申请号：US519334

    申请日：1995-08-25

    申请人： Fumihiko Terayama

    发明人： Fumihiko Terayama

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66

    CPC分类号： G01R31/31855

    摘要： The invention provides a semiconductor device capable of switching drive powers of an output buffer thereof smaller than that for an ordinary operation for detecting even a slight short caused when a component is lying on a wiring pattern, thereby preventing damage of the device in the test even when the wiring pattern between the devices are short-circuited, and further provides a semiconductor device capable of switching drive powers of an output buffer thereof larger than that for an ordinary operation for surely detecting a short between a connection series including the above-mentioned semiconductor device and another connection series including a semiconductor device only having drive powers for the ordinary operation. The invention also provides a method for testing a connection between semiconductor devices capable of surely detecting a short between at least two connection series even on a board where a connection series is included with a conventional semiconductor device only having a drive power for the ordinary operation being mixed, by means of disposing a semiconductor device capable of switching drive powers of an output buffer in at least two levels in another connection series in the upper stream of the current flow, and switching the drive powers of the device to be larger or smaller.

    摘要翻译： 本发明提供了一种半导体器件，其能够将输出缓冲器的驱动功率切换成小于用于检测甚至在组件位于布线图案上时产生的轻微的普通操作的驱动功率，从而防止在测试中的设备的损坏甚至 当器件之间的布线图形短路时，并且还提供能够切换其输出缓冲器的驱动功率大于普通操作的半导体器件，以确保检测包括上述半导体的连接系列之间的短路 装置和包括仅具有用于普通操作的驱动力的半导体器件的另一连接系列。 本发明还提供了一种用于测试半导体器件之间的连接的方法，其能够可靠地检测至少两个连接系列之间的短路，即使在仅具有用于普通操作的驱动功率的常规半导体器件中的连接系列的板上 通过设置能够在当前流的上游中的另一个连接系列中至少两个级别切换输出缓冲器的驱动功率的半导体器件，并且将器件的驱动功率切换到更大或更小。

    Data processor executing memory indirect addressing and register indirect addressing
    6.
    发明授权
    Data processor executing memory indirect addressing and register indirect addressing 失效
    数据处理器执行存储器间接寻址和寄存器间接寻址

    公开(公告)号：US5239633A

    公开(公告)日：1993-08-24

    申请号：US497375

    申请日：1990-05-04

    申请人： Fumihiko Terayama ,  Yuichi Saitou ,  Toyohiko Yoshida

    发明人： Fumihiko Terayama ,  Yuichi Saitou ,  Toyohiko Yoshida

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824

    摘要： A data processor which comprises a pipeline processing mechanism for executing memory indirect addressing and register indirect addressing in an address calculation stage, checks whether or not an instruction writes an operand to a memory or register, makes each stage of the pipeline mechanism hold reservation information thereof in sequence, thereby reduces the frequency of stops of pipeline processing caused by processing of operand address calculation of the following instruction attending on a writing of the operand of the preceding instruction to a memory or register, so that data processing can be execute at a higher efficiency.

    摘要翻译： 一种数据处理器，包括用于在地址计算阶段执行存储器间接寻址和寄存器间接寻址的流水线处理机构，检查指令是否将操作数写入存储器或寄存器，使流水线机构的每一级保持其预留信息 从而降低了由于将前一条指令的操作数写入到存储器或寄存器中的下列指令的操作数地址计算处理引起的流水线处理停止频率，从而数据处理可以在较高的值 效率。