公开(公告)号：US06541840B1

公开(公告)日：2003-04-01

申请号：US09480456

申请日：2000-01-11

申请人： Fumihiko Terayama ,  Seiiti Yamazaki ,  Sintaro Mori

发明人： Fumihiko Terayama ,  Seiiti Yamazaki ,  Sintaro Mori

IPC分类号： H01L2900

CPC分类号： H01L29/92

摘要： An on-chip capacitor is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance is formed between a power source voltage and a grounding voltage formed between said first P-well region and said bottom N-well region. Thus it is not necessary to maintain a device region, to form a capacitance, to form wiring or maintain a wiring region as in a conventional MOS capacitance while it is possible to obtain a required decoupling capacitance.

摘要翻译： 片上电容器设置有P型硅衬底，形成在所述P型硅衬底上的底部N阱区域，彼此相邻的第一P阱和形成在所述底部N阱区域上的第一N阱区域 形成在所述第一N阱区上的第一电极和形成在所述第一P阱区上的第二电极，形成有所述第一N阱区和所述第一P阱区并且形成电容的耦合表面 在所述第一P阱区域和所述底部N阱区域之间形成的电源电压和接地电压之间。 因此，不需要象现有的MOS电容那样保持器件区域，形成电容以形成布线或维持布线区域，同时可以获得所需的去耦电容。