公开(公告)号：US07613903B2

公开(公告)日：2009-11-03

申请号：US09911739

申请日：2001-07-25

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F9/30

CPC分类号： G06F9/30174

摘要： A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an address value for access to the external memory space from the processor core, and fetching the data at the address in the external memory, a translator for translating the nonnative instruction fetched from the external memory into the native instruction, and a select circuit for selectively applying the data read from the external memory space and the instruction prepared by translating the instruction read from the external memory space by the translator to the processor core depending on whether the address value for the access to the external memory space is in a predetermined region or not.

摘要翻译： 数据处理装置包括处理器核心和布置在处理器核心和映射到预定外部存储器空间的外部存储器之间的存储器接口部分。 存储器接口部分包括一个提取电路，用于从处理器核心接收用于访问外部存储器空间的地址值，并且在外部存储器中的地址处取出数据;翻译器，用于将从外部存储器取出的非本地指令转换成 本地指令和用于选择性地应用从外部存储器空间读取的数据的选择电路以及通过将由翻译器从外部存储器空间读取的指令转换为处理器核心而准备的指令，这取决于访问的地址值 外部存储器空间处于预定区域。

公开(公告)号：USRE38679E1

公开(公告)日：2004-12-28

申请号：US09848253

申请日：2001-05-04

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F930

CPC分类号： G06F9/3893 ,  G06F9/30014 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3552 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3889

摘要： A second decoder (114) of an instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives two data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second decoder (114) and the second operation unit (117), a first decoder (113) of the instruction decode unit (119) decodes an operation code for 2 data load, and an operand access unit (104) causes two data (e.g., n bits each) stored in an internal data memory (105) to be transferred in parallel in the form of combined 2n-bit data to a first operation unit (116). Then, two predetermined registers of the register file (115) store the respective n-bit data from the first operation unit (116).

公开(公告)号：US06820252B2

公开(公告)日：2004-11-16

申请号：US09995837

申请日：2001-11-29

申请人： Mamoru Sakamoto ,  Toyohiko Yoshida

发明人： Mamoru Sakamoto ,  Toyohiko Yoshida

IPC分类号： G06F945

CPC分类号： G06F9/30174 ,  G06F9/45504

摘要： A data processor includes a hardware translator converting non-native code into a native code to a processor, a software translator converting non-native code into a native code to the processor by software, and a software interpreter sequentially interpreting a code that is non-native to the processor, and executing the interpreted code using a native code of the processor. The data processor includes a circuit selecting the hardware translator, software translator or software interpreter according to a predetermined criterion for operation.

摘要翻译： 数据处理器包括将非本机代码转换成本地代码到处理器的硬件翻译器，通过软件将非本地代码转换为本地代码到处理器的软件翻译器，以及顺序地解释非代码代码的软件解释器， 并且使用处理器的本地代码来执行解释的代码。 数据处理器包括根据预定的操作标准选择硬件翻译器，软件翻译器或软件解释器的电路。

公开(公告)号：US06757809B1

公开(公告)日：2004-06-29

申请号：US08887681

申请日：1997-07-03

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F900

CPC分类号： G06F9/461 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30149 ,  G06F9/34

摘要： A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a data transfer path which is composed of a plurality of buses between the register file and the data register and which simultaneously transfers two data, in which, in the case where an LDCTX instruction which is the instruction for loading data to more than two register is executed, a combined data of two data each of which is to be loaded in different register is transferred from the operand access unit to the data register, and high order 4 bytes of data and low order 4 bytes of in the data register are simultaneously transfers to two register through two data transfer paths, respectively, and in the case where an STCTX instruction which is the instruction for storing data from more than two register is executed, contents of the two registers are simultaneously transferred to a high order 4 bytes and a low order 4 bytes of the data register, respectively, and two data are combined into one data in the data register, thereafter the combined data is transferred to the operand access unit in one memory accessing.

摘要翻译： 数据处理器具有数据寄存器，该数据寄存器具有用于相对于操作数存取单元输入/输出数据的通用寄存器的宽度的双倍宽度，以及数据传送路径，其由寄存器之间的多条总线组成 文件和数据寄存器，并且同时传送两个数据，其中在作为用于将数据加载到两个以上寄存器的指令的LDCTX指令被执行的情况下，将要加载两个数据的组合数据 在不同的寄存器中从操作数存取单元传送到数据寄存器，数据寄存器中的高位4字节数据和低位4字节分别通过两条数据传输路径同时传送到两个寄存器，在这种情况下 其中执行作为用于存储来自两个以上寄存器的数据的指令的STCTX指令，两个寄存器的内容被同时传送到高位4b ytes和数据寄存器的低位4字节，并且两个数据组合成数据寄存器中的一个数据，之后组合数据在一个存储器访问中被传送到操作数存取单元。

公开(公告)号：US6097113A

公开(公告)日：2000-08-01

申请号：US84949

申请日：1998-05-28

申请人： Eiichi Teraoka ,  Toyohiko Yoshida

发明人： Eiichi Teraoka ,  Toyohiko Yoshida

IPC分类号： H01L29/78 ,  G11C11/408 ,  H01L21/8238 ,  H01L27/092 ,  H03F1/02 ,  H03K19/00 ,  H03K19/094 ,  H01H47/00

CPC分类号： H03K19/0013 ,  H01L27/092 ,  Y10T307/76 ,  Y10T307/826

摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.

摘要翻译： 根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路 用于产生具有不同电压电平的多个电压。 根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

公开(公告)号：US06009205A

公开(公告)日：1999-12-28

申请号：US611051

申请日：1996-03-05

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： H04N19/00 ,  G06T9/00 ,  H03M7/40 ,  H04N1/41 ,  H04N19/42 ,  H04N19/423 ,  H04N19/503 ,  H04N19/61 ,  H04N19/625 ,  H04N19/91 ,  G06K9/36

CPC分类号： G06T9/007

摘要： An image processing device which processes a portion of the decompression process including a lot of comparatively complex operations like an inverse discrete cosine transform by software with using a high-performance, general-purpose processor capable of parallel processing, and the other portion of the decompression process which is comparatively simple but requires frequent access to a memory, e.g., when other frame data is to be read out for processing of encoded interframe predictive image data, or is comparatively simple but substantially hard to process in parallel, e.g., when variable length coded pixel values are to be decoded, by hardware with the use of a specialized peripheral circuit.

摘要翻译： 一种图像处理装置，其通过使用能够并行处理的高性能通用处理器，以及解压缩的另一部分来处理包括大量比较复杂的操作的部分解压缩处理，如通过软件的逆离散余弦变换 过程比较简单，但需要频繁访问存储器，例如当要读取其他帧数据以处理编码帧间预测图像数据时，或者比较简单但是基本上难以并行处理，例如当可变长度 编码像素值将通过使用专用外围电路的硬件进行解码。

公开(公告)号：US5996070A

公开(公告)日：1999-11-30

申请号：US783445

申请日：1997-01-16

申请人： Akira Yamada ,  Toyohiko Yoshida ,  Toru Kengaku

发明人： Akira Yamada ,  Toyohiko Yoshida ,  Toru Kengaku

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/30058 ,  G06F9/30072

摘要： A 3-bit condition execution field in an condition execution instruction stores an encoded value obtained by encoding a condition stored in an general purpose flag indicating to execute the condition execution instruction. A microprocessor has an instruction decode unit 2 comprising a condition execution decode section 401 for decoding a value in the condition execution field and a condition execution judgement section 402 for judging whether or not the decoded result from the condition execution decode section 401 is equal to a condition stored in general purpose flags, and outputting the indication to execute the condition execution instruction when both are equal.

摘要翻译： 条件执行指令中的3位条件执行字段存储通过编码存储在指示执行条件执行指令的通用标志中的条件而获得的编码值。 微处理器具有指令解码单元2，其包括用于解码条件执行区域中的值的条件执行解码单元401和条件执行判断单元402，判定来自条件执行解码单元401的解码结果是否等于 条件存储在通用标志中，并且当两者相等时，输出指示以执行条件执行指令。

公开(公告)号：US5991902A

公开(公告)日：1999-11-23

申请号：US812464

申请日：1997-03-06

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F12/16 ,  G06F11/20 ,  G06F12/08 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H01L27/10

CPC分类号： G11C29/24 ,  G11C29/70

摘要： A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal is inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory. Since the failure in the memory array unit can be relieved, manufacturing yields of the memory apparatus and the data processor including the same are improved.

公开(公告)号：US5941984A

公开(公告)日：1999-08-24

申请号：US857461

申请日：1997-05-16

申请人： Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

发明人： Atsushi Mohri ,  Akira Yamada ,  Toyohiko Yoshida

IPC分类号： G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3828 ,  G06F9/3889

摘要： A VLIW microprocessor in which bypaths for transferring data among pipelines are incorporated between a plurality of execution units such as a memory access unit and an integer operation unit. The data on the bypaths is directly transferred to target units according to a control signal generated by a bypath processing control circuit.

摘要翻译： 一种VLIW微处理器，其中用于在管线之间传送数据的逐行路径被并入在诸如存储器存取单元和整数运算单元的多个执行单元之间。 根据由路径处理控制电路产生的控制信号，将路径上的数据直接传送到目标单元。

公开(公告)号：US5761470A

公开(公告)日：1998-06-02

申请号：US574283

申请日：1995-12-18

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30145 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3885

摘要： In a data processor, using a format field which specifies the number of operation fields of an instruction code and all order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.

摘要翻译： 在数据处理器中，使用指定指令代码的操作字段的数量的格式字段和操作的所有执行顺序，灵活地控制操作次数和操作执行次序，并且减少空操作的必要性 并且解码器并行操作，每个仅解码具有与操作执行机构相关的特定功能的一个操作，使得指令代码的操作字段由多个解码器并行解码。 虽然数据处理器基本上是一个VLIW型数据处理器，但操作领域可以指定更多类型的操作，并且由于操作字段的数量和操作执行的顺序被灵活地控制，并且必须 通过指定操作次数和操作执行顺序的格式字段来减少空操作。