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    Data processor for modifying and executing operation of instruction code
    1.
    发明申请
    Data processor for modifying and executing operation of instruction code 审中-公开
    用于修改和执行指令代码操作的数据处理器

    公开(公告)号：US20080082800A1

    公开(公告)日：2008-04-03

    申请号：US11976568

    申请日：2007-10-25

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/318

    CPC分类号： G06F9/3001 ,  G06F9/30185 ,  G06F9/34 ,  G06F9/382 ,  G06F9/3853

    摘要： A MOD_SAT instruction indicating that a 16 bit saturation is to be carried out with respect to the operation of one of instructions executed in parallel is placed in the left container and an ADD instruction is placed in the right container. When the instruction decode unit decodes these instructions, the instruction decode unit indicates that the instruction execution unit executes the ADD instruction accompanying a saturation process. Accordingly, the operation of a great number of instructions can be modified by combining instructions and, therefore, the basic instruction length can be made short and it becomes possible to increase the code efficiency.

    摘要翻译： 指示相对于并行执行的一个指令的操作执行16位饱和的MOD_SAT指令被放置在左容器中，并且ADD指令被放置在右容器中。 当指令解码单元解码这些指令时，指令解码单元指示指令执行单元执行伴随饱和处理的ADD指令。 因此，可以通过组合指令来修改大量指令的操作，因此可以缩短基本指令长度，并且可以提高代码效率。

    Data processor speeding up repeat processing by inhibiting remaining instructions after a break in a repeat block
    2.
    发明授权
    Data processor speeding up repeat processing by inhibiting remaining instructions after a break in a repeat block 有权
    数据处理器通过在重复块中断之后禁止剩余指令来加速重复处理

    公开(公告)号：US07010677B2

    公开(公告)日：2006-03-07

    申请号：US09921554

    申请日：2001-08-06

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/40

    CPC分类号： G06F9/30065 ,  G06F9/325 ,  G06F9/4484

    摘要： A comparator 172 compares the value held in an RPT_B register 171 with the address of the instruction which is held in an IA register 181 and is to be fetched next, and outputs coincidence information indicating whether these value coincide with each other. Based on the coincidence information, a control part 112 generates hardware-wise a control signal for switching an instruction processing sequence to the next instruction of a repeat block in the last repeat processing of the repeat block.

    摘要翻译： 比较器172将保持在RPT_B寄存器171中的值与保持在IA寄存器181中的指令的地址相比较，并且输出表示这些值是否一致的一致信息。 基于一致信息，控制部分112在重复块的最后重复处理中硬件地产生用于将指令处理序列切换到重复块的下一条指令的控制信号。

    Data processor
    3.
    发明申请
    Data processor 审中-公开
    数据处理器

    公开(公告)号：US20050283589A1

    公开(公告)日：2005-12-22

    申请号：US11152723

    申请日：2005-06-15

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/32

    CPC分类号： G06F9/30134 ,  G06F9/30014 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/384

    摘要： An input pointer update circuit updates an input pointer in response to the value of an RBC latch, the input pointer of a BIP latch and input pointer update information from an instruction decoding unit (first decoder) when the value of an RM latch is “1”. An output pointer update circuit updates an output pointer in response to the value of the RBC latch, the output pointer of a BOP latch and output pointer update information from the instruction decoding unit (the first decoder or a second decoder). A register mapping circuit maps a logical register number to a physical register number on the basis of output information from the input pointer update circuit, the output pointer update circuit etc.

    摘要翻译： 当RM锁存器的值为“1”时，输入指针更新电路响应于RBC锁存器的值，BIP锁存器的输入指针和来自指令解码单元（第一解码器）的输入指针更新信息来更新输入指针 “。 响应于RBC锁存器的值，BOP锁存器的输出指针和来自指令解码单元（第一解码器或第二解码器）的输出指针更新信息，输出指针更新电路更新输出指针。 寄存器映射电路基于来自输入指针更新电路，输出指针更新电路等的输出信息，将逻辑寄存器号映射到物理寄存器号。

    Data processor
    4.
    发明授权
    Data processor 失效
    数据处理器

    公开(公告)号：US06484253B1

    公开(公告)日：2002-11-19

    申请号：US09355024

    申请日：1999-07-23

    申请人： Masahito Matsuo

    发明人： Masahito Matsuo

    IPC分类号： G06F930

    CPC分类号： G06F9/30014 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/325 ,  G06F9/34 ,  G06F9/3552 ,  G06F9/3822 ,  G06F9/3853

    摘要： The present invention relates to a data processor, and particularly in a data processor performing condition execution on the basis of flag information, aims at obtaining a data processor having excellent code efficiency, which can reduce branch penalty. In order to attain the aforementioned object, it is so structured that, when a first instruction decoded in a first decoder is an execution condition specifying instruction specifying the execution condition for a pair of second instructions executed in parallel, a first execution condition determination unit performs determination of the execution condition for the second instructions defined by the execution condition specifying instruction on the basis of the flag information and controls assertion/non-assertion of an execution inhibit signal on the basis of whether the execution condition defined by the execution condition specifying instruction is satisfied or not.

    摘要翻译： 本发明涉及一种数据处理器，特别是在基于标志信息执行条件执行的数据处理器中，旨在获得具有优异代码效率的数据处理器，这可以减少分支损失。 为了实现上述目的，结构是，当在第一解码器中解码的第一指令是指定并行执行的一对第二指令的执行条件的执行条件指定指令时，第一执行条件确定单元执行 基于标志信息确定由执行条件指定指令定义的第二指令的执行条件，并且基于执行条件指定指令定义的执行条件来控制执行禁止信号的断言/非断言 是否满意。

    Data processor
    5.
    发明授权
    Data processor 失效

    公开(公告)号：US6151673A

    公开(公告)日：2000-11-21

    申请号：US359843

    申请日：1999-07-23

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

    摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

    Data processor
    6.
    发明授权
    Data processor 失效

    公开(公告)号：US5978904A

    公开(公告)日：1999-11-02

    申请号：US996787

    申请日：1997-12-23

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

    摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

    Pipeline processor, with a return address stack and two stack pointers, for storing pre-return processed addresses
    8.
    发明授权
    Pipeline processor, with a return address stack and two stack pointers, for storing pre-return processed addresses 失效
    管道处理器，具有返回地址堆栈和两个堆栈指针，用于存储预返回处理的地址

    公开(公告)号：US5526498A

    公开(公告)日：1996-06-11

    申请号：US181353

    申请日：1994-01-13

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

    摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

    摘要翻译： 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

    Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address
    9.
    发明授权
    Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address 失效
    管道处理器，返回地址堆栈仅存储用于判断有效性的预处理地址和未处理地址的校正

    公开(公告)号：US5355459A

    公开(公告)日：1994-10-11

    申请号：US953414

    申请日：1992-09-29

    申请人： Masahito Matsuo ,  Toyohiko Yoshida

    发明人： Masahito Matsuo ,  Toyohiko Yoshida

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40 ,  G06F9/42

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

    摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

    摘要翻译： 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

    System for processing parameters in instructions of different format to execute the instructions using same microinstructions
    10.
    发明授权
    System for processing parameters in instructions of different format to execute the instructions using same microinstructions 失效
    用于处理不同格式指令中的参数的系统，以使用相同的微指令执行指令

    公开(公告)号：US5321821A

    公开(公告)日：1994-06-14

    申请号：US954096

    申请日：1992-09-29

    申请人： Fujio Itomitsu ,  Masahito Matsuo

    发明人： Fujio Itomitsu ,  Masahito Matsuo

    IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/318

    CPC分类号： G06F9/30192 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/342

    摘要： A device and method for generating execution controlling information (operation designating parameter) for an instruction execution means is provided. The device operates by selecting and composing a parameter (bit field) selected from among the bits of an instruction code and a parameter obtained as a result of decoding the instruction to be executed. The process makes it possible to reduce the size of a micro ROM by processing one instruction having various formats by the same micro-instruction.

    摘要翻译： 提供了一种用于生成用于指令执行装置的执行控制信息（操作指定参数）的装置和方法。 该装置通过选择和组合从指令码的位中选择的参数（位域）和作为对要执行的指令进行解码的结果而获得的参数进行操作。 该处理使得可以通过相同的微指令处理具有各种格式的一个指令来减小微ROM的大小。