公开(公告)号：US06408385B1

公开(公告)日：2002-06-18

申请号：US09602830

申请日：2000-06-23

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F940

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

摘要翻译： 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

公开(公告)号：US5485587A

公开(公告)日：1996-01-16

申请号：US10085

申请日：1993-01-27

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

公开(公告)号：US5386580A

公开(公告)日：1995-01-31

申请号：US819545

申请日：1992-01-10

申请人： Toyohiko Yoshida ,  Masahito Matsuo

发明人： Toyohiko Yoshida ,  Masahito Matsuo

IPC分类号： G06F9/22 ,  G06F9/28 ,  G06F9/30 ,  G06F9/34 ,  G06F9/345 ,  G06F9/35 ,  G06F9/38

CPC分类号： G06F9/345 ,  G06F9/34

摘要： A data processor which comprises: an instruction decoding unit for decoding the instruction; an operand address calculating unit having an adder and an output latch holding the added result and calculating addresses of plural memory operands, in accordance with address calculation control code outputted from the instruction decoding unit; and an instruction executing unit for executing the instruction, in accordance with the operand address outputted from the operand address calculating unit and an operation control code outputted from the instruction decoding unit; and is capable of executing the plural data operating instruction for processing plural data at high efficiency, by performing address calculation of the plural operands by the operand address calculating unit before executing the instruction by the instruction executing unit.

摘要翻译： 一种数据处理器，包括：指令解码单元，用于解码指令; 操作数地址计算单元，具有根据从指令解码单元输出的地址计算控制码，具有加法器和保存相加结果的输出锁存器以及计算多个存储器操作数的地址; 以及指令执行单元，用于根据从操作数地址计算单元输出的操作数地址和从指令解码单元输出的操作控制代码执行指令; 并且能够通过由指令执行单元执行指令之前通过操作数地址计算单元执行多个操作数的地址计算，来执行用于高效率处理多个数据的多个数据操作指令。

公开(公告)号：US5349681A

公开(公告)日：1994-09-20

申请号：US821802

申请日：1992-01-16

申请人： Toyohiko Yoshida ,  Masahito Matsuo

发明人： Toyohiko Yoshida ,  Masahito Matsuo

IPC分类号： G06F9/30 ,  G06F7/74 ,  G06F9/305 ,  G06F9/308 ,  G06F9/34 ,  G06F12/00 ,  G06F9/312

CPC分类号： G06F7/74 ,  G06F9/30018

摘要： A bit searching circuit includes an offset value designating circuit, a bit position detecting circuit, a count circuit, and a search-end detecting circuit. The offset value designating circuit outputs an offset value indicating a search-start position. The bit position detecting circuit searches for the first bit position which has a first binary value, in a search field between the bit position designated by the offset value and a last bit position in a bit string. The count circuit counts the number of bits in the search field having the first binary value. The search-end detecting circuit detects the end of search processing by subtracting the bit counts detected by the bit position detecting circuit from the count value counted by the count circuit until the result is zero. A data processor using such a bit searching circuit includes a control unit and an instruction execution unit. The control unit includes a decoding circuit, decoding an operation code field of an instruction for operating on plural data where the instruction includes a register list indicating the register numbers storing data to be operated on. The bit searching circuit searches the register list represented by a bit string field consisting of binary values, and controls execution of the instruction. The instruction executing unit executes the instruction.

摘要翻译： 位搜索电路包括偏移值指定电路，位位置检测电路，计数电路和搜索结束检测电路。 偏移值指定电路输出表示搜索开始位置的偏移值。 比特位置检测电路在由偏移值指定的比特位置和比特串中的最后比特位置之间的搜索字段中搜索具有第一二进制值的第一比特位置。 计数电路对具有第一二进制值的搜索字段中的位数进行计数。 搜索结束检测电路通过从由计数电路计数的计数值减去由比特位置检测电路检测的比特计数直到结果为零来检测搜索结束结束。 使用这种位搜索电路的数据处理器包括控制单元和指令执行单元。 控制单元包括解码电路，用于解码用于操作多个数据的指令的操作码字段，其中该指令包括指示存储要操作的数据的寄存器号的寄存器列表。 位搜索电路搜索由由二进制值组成的位串字段表示的寄存器列表，并控制指令的执行。 指令执行单元执行指令。

公开(公告)号：US4858104A

公开(公告)日：1989-08-15

申请号：US143547

申请日：1988-01-13

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/38

CPC分类号： G06F9/3844

摘要： A branch prediction for predicting, prior to executing a given branch instruction, whether the branch condition of the given branch instruction will be established, utilizes an address of an instruction that precedes the given branch instruction to access the branch prediction information for the given branch instruction from a branch prediction table.

摘要翻译： 一种分支预测，用于在执行给定的分支指令之前，预测给定分支指令的分支条件是否将被建立，利用在给定分支指令之前的指令的地址来访问给定分支指令的分支预测信息 从分支预测表。

公开(公告)号：US6058471A

公开(公告)日：2000-05-02

申请号：US759500

申请日：1996-12-04

申请人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F11/28 ,  G06F11/36

CPC分类号： G06F9/3865 ,  G06F11/28 ,  G06F11/3648 ,  G06F9/3001 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3875

摘要： A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

摘要翻译： 一种数据处理系统，能够通过与执行指令的情况相同的处理从异常处理中正确地返回，即使在指令处理的中途发生异常，也无需特别的控制，能够选择模式 用于在调试或测试中逐个执行指令，使得与简单控制并行地执行多个指令。

公开(公告)号：US5812809A

公开(公告)日：1998-09-22

申请号：US759498

申请日：1996-12-04

申请人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F11/28 ,  G06F11/36

CPC分类号： G06F9/3865 ,  G06F11/28 ,  G06F11/3648 ,  G06F9/3001 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3875

摘要： A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

摘要翻译： 一种数据处理系统，能够通过与执行指令的情况相同的处理从异常处理中正确地返回，即使在指令处理的中途发生异常，也无需特别的控制，能够选择模式 用于在调试或测试中逐个执行指令，使得与简单控制并行地执行多个指令。

公开(公告)号：US5649145A

公开(公告)日：1997-07-15

申请号：US537001

申请日：1995-09-29

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

公开(公告)号：US5617550A

公开(公告)日：1997-04-01

申请号：US535871

申请日：1995-09-29

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/322 ,  G06F9/3842

摘要： A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions fetched from the instruction fetch unit 111; an instruction execution unit which executes the instructions on the basis of the decoding result by the instruction decoding unit 112; a program counter (DPC) 29 which holds an address of the instruction being decoded in the instruction decoding unit 112; and a branch target address calculation unit 1 which is connected to the instruction fetch unit 111 and the program counter (DPC) 29, adds a value of a branch displacement field transferred from the instruction fetch unit 111 and the instruction address transferred from the program counter (DPC) 29, and transfers the addition result to the instruction fetch unit 111, so that jump instruction can be processed efficiently by pipeline processing.

摘要翻译： 一种数据处理器，包括：指令提取单元111，其从存储指令的存储器中取出指令; 指令解码单元112，对从指令获取单元111取出的指令进行解码; 指令执行单元，其基于指令解码单元112的解码结果执行指令; 程序计数器（DPC）29，其保持在指令解码单元112中解码的指令的地址; 和连接到指令提取单元111和程序计数器（DPC）29的分支目标地址计算单元1相加从指令提取单元111传送的分支位移字段的值和从程序计数器传送的指令地址 （DPC）29，并将相加结果传送到指令提取单元111，使得可以通过流水线处理有效地处理跳转指令。

公开(公告)号：US4847753A

公开(公告)日：1989-07-11

申请号：US72708

申请日：1987-07-13

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3806 ,  G06F9/3861

摘要： A pipelined computer includes an instruction cache connected to an instruction prefetch queue for storing a target address and a target instruction, with the address of a branch instruction taken as an index, and a comparator for comparing a predicted target address stored in the instruction cache with a real target address determined upon execution of the branch instruction. When both the target addresses agree in the comparator, the decoding unit and the instruction prefetch queue continue pipeline processing without alteration.

摘要翻译： 流水线计算机包括连接到指令预取队列的指令高速缓存，用于存储目标地址和目标指令，分支指令的地址作为索引，以及比较器，用于将存储在指令高速缓存中的预测目标地址与 在执行分支指令时确定的实际目标地址。 当目标地址在比较器中都一致时，解码单元和指令预取队列继续进行流水线处理而不改变。