公开(公告)号：US5276889A

公开(公告)日：1994-01-04

申请号：US543273

申请日：1990-06-25

Applicant: Taketora Shiraishi ,  Eiichi Teraoka ,  Toru Kengaku

Inventor： Taketora Shiraishi ,  Eiichi Teraoka ,  Toru Kengaku

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38 ,  G06F15/78

CPC classification number: G06F1/3215 ,  G06F1/3275 ,  G06F9/3836 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/32

Abstract: A microprocessor, including a synchronous type memory having several parts, includes a power saving feature that places at least some parts of the memory in a non-operating state when instructions not requiring access to the memory are executed. An enable signal is generated when access is not required and a signal supplying circuit supplies a synchronous signal when the enable signal is not generated and supplies a signal in a predetermined state to place at least some parts or all parts of the memory in the non-operating state to reduce power consumption.

Abstract translation: 包括具有若干部分的同步型存储器的微处理器包括省电功能，其中当执行不需要访问存储器的指令时，将存储器的至少一些部分置于非操作状态。 当不需要访问时产生使能信号，并且当不产生使能信号时信号供给电路提供同步信号，并且提供处于预定状态的信号以将存储器的至少一部分或全部部分放置在非易失性存储器中， 运行状态降低功耗。

公开(公告)号：US4870609A

公开(公告)日：1989-09-26

申请号：US113612

申请日：1987-10-26

Applicant: Ikuo Yasui ,  Yukihiko Shimazu ,  Toru Kengaku

Inventor： Ikuo Yasui ,  Yukihiko Shimazu ,  Toru Kengaku

IPC: G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/508

CPC classification number: G06F7/503

Abstract: The operation speed of a full adder is increased by avoiding the necessity of forming the inverse signal for adder operation and deleting the time required for passing through an inverter.

Abstract translation: 通过避免形成用于加法器操作的反向信号和删除通过逆变器所需的时间的必要性，增加了全加器的操作速度。

公开(公告)号：US20090144517A1

公开(公告)日：2009-06-04

申请号：US12277493

申请日：2008-11-25

Applicant: Ichiki HOMMA ,  Toru Kengaku

Inventor： Ichiki HOMMA ,  Toru Kengaku

IPC: G06F12/00

CPC classification number: G06F13/28

Abstract: Decrease in throughput performance called a “jamming” in a memory device is prevented. There is provided a timing generation part which gives, based on a request signal outputted for each unit of the data processing from a data processing part, an output timing for a burst transfer request to a burst transfer request generation part. Based on the relationship in size between a lapsed time from the output of the burst transfer request to the activation of the request signal and a time specified by a set threshold value of a threshold value register, the timing generation part controls output timing for a burst transfer request. When the lapsed time exceeds the time specified by a maximum threshold value, the burst transfer request generation part is given an output timing for the burst transfer request without waiting for the activation of the request signal. As a result, when the issuance of the request signal is delayed, a next burst transfer request can be given to the memory device without waiting for the issuance but preceding it.

Abstract translation: 防止在存储器件中称为“干扰”的吞吐量性能降低。 提供了一种定时生成部件，其基于从数据处理部分对每个单位的数据处理输出的请求信号，向突发传送请求生成部分提供突发传送请求的输出定时。 基于从突发传送请求的输出到请求信号的激活的经过时间与由阈值寄存器的设定阈值指定的时间之间的大小关系，定时生成部控制突发的输出定时 转移请求。 当经过的时间超过由最大阈值指定的时间时，突发传送请求生成部分被给予突发传送请求的输出定时，而不等待激活请求信号。 结果，当请求信号的发出被延迟时，可以向存储设备提供下一个突发传送请求，而不必等待发出，而在其之前。

公开(公告)号：US07483593B2

公开(公告)日：2009-01-27

申请号：US11892580

申请日：2007-08-24

Applicant: Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

Inventor： Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

IPC: G06K9/32 ,  H04N9/74

CPC classification number: G06T1/60 ,  G06T3/40

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract translation: 当由行数计数单元计数的行号对应于规定行号时，传送源地址产生单元将偏移地址设置单元中设置的偏移地址添加到各个传送源地址，作为地址输出到存储器。 DMA控制单元根据由传送源地址生成单元生成的传送源地址和由传送目的地地址生成单元生成的传送目的地地址进行DMA传送。 因此，图像数据的快速放大/缩小成为可能。

公开(公告)号：US20080044106A1

公开(公告)日：2008-02-21

申请号：US11892580

申请日：2007-08-24

Applicant: Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

Inventor： Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

IPC: G06T3/40

CPC classification number: G06T1/60 ,  G06T3/40

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract translation: 当由行数计数单元计数的行号对应于规定行号时，传送源地址产生单元将偏移地址设置单元中设置的偏移地址添加到各个传送源地址，作为地址输出到存储器。 DMA控制单元根据由传送源地址生成单元生成的传送源地址和由传送目的地地址生成单元生成的传送目的地地址进行DMA传送。 因此，图像数据的快速放大/缩小成为可能。

公开(公告)号：US5301137A

公开(公告)日：1994-04-05

申请号：US47757

申请日：1993-04-14

Applicant: Takahiro Matsuo ,  Toshiki Fujiyama ,  Toru Kengaku

Inventor： Takahiro Matsuo ,  Toshiki Fujiyama ,  Toru Kengaku

IPC: G06F7/487 ,  G06F7/52 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F17/10 ,  G06F7/38

CPC classification number: G06F7/483 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/30181

Abstract: An operation circuit for performing either fixed or floating point mathematical operations, having a mode control function for a multiplier including a multiplier, an arithmetic logic unit (ALU) and a signal generating circuit. A signal specifying the operating mode of the ALU, either a fixed point mode or a floating point mode is used by the signal generating circuit for generating either a fixed point multiplication signal or a floating point multiplication signal to control the multiplier, respectively.

Abstract translation: 一种用于执行固定或浮点数学运算的运算电路，具有用于包括乘法器的乘法器的模式控制功能，运算逻辑单元（ALU）和信号产生电路。 信号发生电路使用指定ALU的操作模式的信号，即固定点模式或浮点模式，用于分别产生固定点乘法信号或浮点乘法信号以控制乘法器。

公开(公告)号：US5191547A

公开(公告)日：1993-03-02

申请号：US564808

申请日：1990-08-08

Applicant: Koji Kawamoto ,  Toru Kengaku ,  Eiichi Teraoka ,  Tetsuaki Oga ,  Hiroichi Ishida

Inventor： Koji Kawamoto ,  Toru Kengaku ,  Eiichi Teraoka ,  Tetsuaki Oga ,  Hiroichi Ishida

IPC: H03H17/00 ,  G06F17/10 ,  H03H17/06

CPC classification number: H03H17/0664 ,  G06F17/10 ,  H03H2218/10

Abstract: A decimation type digital filter which utilizes the thinned-out signal of a finite impulse response (FIR) filter having N taps for processing the signal by the product sum operation of filter coefficients and the input signals inputted at every first period, in which, on the basis of the ratio K between a first period which is the input signal period and an output signal period and the number of taps N, M (a value obtained by raising below the decimal point of N/K) registers are provided and M successive output signals are processed by the product sum operation in parallel by respective registers, whereby the input signal is not necessarily to be held, a capacity of the register may be minimized and processing may be effected once for each register during the first period or by M number of times of product sum operation in total, thus the operating speed can be reduced to 1/K and the capacity and the operating speed can be optimized.

Abstract translation: 一种抽取式数字滤波器，其利用具有N个抽头的有限脉冲响应（FIR）滤波器的稀疏信号通过滤波器系数的乘积和运算和每个第一周期输入的输入信号来处理该信号，其中， 提供作为输入信号周期的第一周期与输出信号周期之间的比率K与抽头数N，M（通过升高到小于N / K的小数点而获得的值）之间的比率K的基础，M连续 输出信号由相应的寄存器并行处理，由此输入信号不一定被保持，寄存器的容量可以最小化，并且可以在第一周期期间对每个寄存器执行一次处理，或者通过M 产品总计运算次数，可以将运行速度降低到1 / K，可以优化运行速度和运行速度。

公开(公告)号：US07298924B2

公开(公告)日：2007-11-20

申请号：US10667354

申请日：2003-09-23

Applicant: Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

Inventor： Tomohiro Sakurai ,  Toru Kengaku ,  Tatsuya Ueda

IPC: G06K9/32 ,  H04N9/74

CPC classification number: G06T1/60 ,  G06T3/40

Abstract: When a line number counted by a line number counting unit corresponds to a prescribed line number, a transfer source address generating unit adds an offset address set in an offset address setting unit to respective transfer source addresses to output as addresses to a memory. A DMA control unit controls DMA transfer in accordance with a transfer source address generated by the transfer source address generating unit and a transfer destination address generated by a transfer destination address generating unit. Thus, rapid enlargement/reduction of image data becomes possible.

Abstract translation: 当由行数计数单元计数的行号对应于规定行号时，传送源地址产生单元将偏移地址设置单元中设置的偏移地址添加到各个传送源地址，作为地址输出到存储器。 DMA控制单元根据由传送源地址生成单元生成的传送源地址和由传送目的地地址生成单元生成的传送目的地地址进行DMA传送。 因此，图像数据的快速放大/缩小成为可能。

公开(公告)号：US5996070A

公开(公告)日：1999-11-30

申请号：US783445

申请日：1997-01-16

Applicant: Akira Yamada ,  Toyohiko Yoshida ,  Toru Kengaku

Inventor： Akira Yamada ,  Toyohiko Yoshida ,  Toru Kengaku

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30094 ,  G06F9/30058 ,  G06F9/30072

Abstract: A 3-bit condition execution field in an condition execution instruction stores an encoded value obtained by encoding a condition stored in an general purpose flag indicating to execute the condition execution instruction. A microprocessor has an instruction decode unit 2 comprising a condition execution decode section 401 for decoding a value in the condition execution field and a condition execution judgement section 402 for judging whether or not the decoded result from the condition execution decode section 401 is equal to a condition stored in general purpose flags, and outputting the indication to execute the condition execution instruction when both are equal.

Abstract translation: 条件执行指令中的3位条件执行字段存储通过编码存储在指示执行条件执行指令的通用标志中的条件而获得的编码值。 微处理器具有指令解码单元2，其包括用于解码条件执行区域中的值的条件执行解码单元401和条件执行判断单元402，判定来自条件执行解码单元401的解码结果是否等于 条件存储在通用标志中，并且当两者相等时，输出指示以执行条件执行指令。

公开(公告)号：US5317529A

公开(公告)日：1994-05-31

申请号：US859208

申请日：1992-03-27

Applicant: Eiichi Teraoka ,  Toru Kengaku ,  Hiroichi Ishida

Inventor： Eiichi Teraoka ,  Toru Kengaku ,  Hiroichi Ishida

IPC: H03M1/00 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H03M3/00 ,  G06F15/31

CPC classification number: H03H17/0657 ,  H03H17/0664 ,  H03H17/0685 ,  H03H2218/08 ,  H03H2218/085

Abstract: An A/D-D/A converting apparatus, in which a multiplier is omitted by storing the multiplied result of a filter coefficient and a digital signal in advance and reading it out responsive to the inputted digital signal, in view of the point that filter characteristics of digital filters of an A/D converting unit and a D/A converting unit are equal one another, memories which are coefficient generating devices are used in common, and further, in view of the point :hat processing contents of respective digital filters are equal, a multiplier and an accumulator constituting the digital filter are used in common to reduce a circuit configuration considerably.

Abstract translation: A / DD / A转换装置，其中通过根据输入的数字信号预先存储滤波器系数和数字信号的相乘结果而省略乘法器，考虑到滤波器特性 A / D转换单元和D / A转换单元的数字滤波器彼此相等，作为系数产生装置的存储器是共同使用的，此外，考虑到各个数字滤波器的帽子处理内容相等 ，共同地使用构成数字滤波器的乘法器和累加器来显着地减少电路配置。