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    Methods of forming integrated circuit devices having stacked gate electrodes
    2.
    发明授权
    Methods of forming integrated circuit devices having stacked gate electrodes 有权
    形成具有层叠栅电极的集成电路器件的方法

    公开(公告)号：US07998810B2

    公开(公告)日：2011-08-16

    申请号：US12424922

    申请日：2009-04-16

    Applicant: Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    Inventor： Byung-hee Kim ,  Gil-heyun Choi ,  Sang-woo Lee ,  Chang-won Lee ,  Jin-ho Park ,  Eun-ji Jung ,  Jeong-gil Lee

    IPC: H01L21/336

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/66545

    Abstract: A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer.

    Abstract translation: 提供一种形成半导体器件的栅电极的方法，所述方法包括：形成多个堆叠结构，每个堆叠结构包括隧道介电层，用于浮置栅极的第一硅层，栅极间介电层，用于控制的第二硅层 栅极和掩模图案，以所述顺序在半导体衬底上; 在所述多个堆叠结构之间形成第一层间电介质层，使得所述掩模图案的顶表面露出; 选择性地去除其顶表面暴露的掩模图案; 在去除所述硬盘层的区域中形成第三硅层，以及形成包含所述第三硅层和所述第二硅层的硅层; 使第一层间电介质层凹陷，使得硅层的上部突出在第一层间介电层上; 以及在所述硅层的上部形成金属硅化物层。

    Semiconductor devices having stacked structures
    4.
    发明授权
    Semiconductor devices having stacked structures 失效
    具有堆叠结构的半导体器件

    公开(公告)号：US07936024B2

    公开(公告)日：2011-05-03

    申请号：US12204420

    申请日：2008-09-04

    Applicant: Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    Inventor： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC: H01L29/76

    CPC classification number: H01L21/8221 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76898 ,  H01L27/0688 ,  Y10S257/903

    Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern. After removing portions of the single crystal semiconductor plug, a single crystal semiconductor layer may be formed on the interlayer insulating layer and on the single crystal semiconductor contact pattern. A second interlayer insulating layer may be formed on the single crystal semiconductor layer, and a common contact hole may be formed through the second interlayer insulating layer, through the single crystal semiconductor layer, and through the first interlayer insulating layer to expose a portion of semiconductor substrate. In addition, a conductive contact plug may be formed in the common contact hole in contact with the semiconductor substrate. Related devices are also discussed.

    Abstract translation: 形成半导体器件的方法可以包括在半导体衬底上形成层间绝缘层，并且层间绝缘层可以具有暴露半导体衬底的一部分的接触孔。 可以在接触孔中和在与半导体衬底相对的接触孔附近的层间绝缘层的部分上形成单晶半导体插塞，并且与半导体衬底相对的部分层间绝缘层可以不含单晶半导体插头。 可以去除接触孔中的单晶半导体插塞的部分，同时将单晶半导体插塞的部分保持在与接触孔相邻的层间绝缘层的部分上作为单晶半导体接触图案。 在去除单晶半导体插头的部分之后，可以在层间绝缘层和单晶半导体接触图案上形成单晶半导体层。 可以在单晶半导体层上形成第二层间绝缘层，并且可以通过单晶半导体层通过第二层间绝缘层形成公共接触孔，并且通过第一层间绝缘层暴露半导体的一部分 基质。 此外，可以在与半导体衬底接触的公共接触孔中形成导电接触插塞。 还讨论了相关设备。

    METHOD OF FORMING BURIED GATE ELECTRODE
    5.
    发明申请
    METHOD OF FORMING BURIED GATE ELECTRODE 失效
    形成基底电极的方法

    公开(公告)号：US20100240184A1

    公开(公告)日：2010-09-23

    申请号：US12626959

    申请日：2009-11-30

    Applicant: Eun-ji Jung ,  Hyun-soo Kim ,  Byung-hee Kim ,  Dae-yong Kim ,  Woong-hee Sohn ,  Kwang-jin Moon ,  Jang-hee Lee ,  Min-sang Song ,  Eun-ok Lee

    Inventor： Eun-ji Jung ,  Hyun-soo Kim ,  Byung-hee Kim ,  Dae-yong Kim ,  Woong-hee Sohn ,  Kwang-jin Moon ,  Jang-hee Lee ,  Min-sang Song ,  Eun-ok Lee

    IPC: H01L21/336 ,  H01L21/28

    CPC classification number: H01L21/28052 ,  H01L29/4236

    Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

    Abstract translation: 形成掩埋栅电极的方法防止在栅电极的硅化物层中形成空隙。 该方法开始于在半导体衬底中形成沟槽，在已经形成沟槽的半导体上形成共形栅极氧化层，在栅极氧化层上形成第一栅电极层，在第一栅电极上形成硅层 层填补沟槽。 然后，去除第一栅极电极层的一部分以形成暴露硅层的侧表面的一部分的凹部。 然后在包括硅层的半导体衬底上形成金属层。 接下来，半导体衬底退火，同时暴露硅层的侧表面以在硅层上形成金属硅化物层。

    Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors
    9.
    发明授权
    Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors 有权
    包括上和下晶体管的半导体器件和上和下晶体管之间的互连

    公开(公告)号：US07381989B2

    公开(公告)日：2008-06-03

    申请号：US11368418

    申请日：2006-03-07

    Applicant: Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    Inventor： Hyun-Su Kim ,  Gil-Heyun Choi ,  Jong-Ho Yun ,  Sug-Woo Jung ,  Eun-Ji Jung

    IPC: H01L29/76 ,  H01L31/036 ,  H01L31/112

    CPC classification number: H01L27/0688 ,  H01L21/8221

    Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

    Abstract translation: 叠层半导体器件包括形成在半导体衬底上的下晶体管，形成在半导体衬底上的下层晶体管上的下层间绝缘膜，形成在下晶体管上的下层间绝缘膜上的上晶体管，以及上层间绝缘膜 形成在上层晶体管上的较低层间绝缘膜上。 叠层半导体器件还包括连接在下晶体管的漏极或源极区域与上部晶体管的源极或漏极区域之间的接触插塞以及连接到上部晶体管的源极或漏极区域的侧面的延伸层 以扩大上部晶体管的源极或漏极区域与接触插塞的一侧之间的接触面积。

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