Invention Grant
- Patent Title: Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors
- Patent Title (中): 包括上和下晶体管的半导体器件和上和下晶体管之间的互连
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Application No.: US11368418Application Date: 2006-03-07
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Publication No.: US07381989B2Publication Date: 2008-06-03
- Inventor: Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
- Applicant: Hyun-Su Kim , Gil-Heyun Choi , Jong-Ho Yun , Sug-Woo Jung , Eun-Ji Jung
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2005-0018781 20050307
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L31/036 ; H01L31/112

Abstract:
A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.
Public/Granted literature
- US20060197117A1 Stacked semiconductor device and method of fabrication Public/Granted day:2006-09-07
Information query
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