公开(公告)号：US20110089400A1

公开(公告)日：2011-04-21

申请号：US12937871

申请日：2009-04-15

Applicant: Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind

Inventor： Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind

IPC: H01L33/06 ,  B82Y99/00 ,  B82Y20/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/7391 ,  H01L29/775 ,  H01L33/0041 ,  H01L33/18

Abstract: The present invention provides a semiconductor device comprising at least a first semiconductor nanowire (105) having a first lengthwise region (121) of a first conductivity type, a second lengthwise region (122) of a second conductivity type, and at least a first wrap gate electrode (111) arranged at the first region (121) of the nanowire (105) in order to vary the charge carrier concentration in the first lengthwise region (121) when a voltage is applied to the first wrap gate electrode (111). Preferably a second wrap gate electrode (112) is arranged at the second lengthwise region (122). Thereby tuneable artificial junctions (114) can be accomplished without substantial doping of the nanowire (105).

Abstract translation: 本发明提供一种半导体器件，其包括至少第一半导体纳米线（105），其具有第一导电类型的第一纵向区域（121），第二导电类型的第二纵向区域（122）和至少第一包层 栅极电极（111），布置在纳米线（105）的第一区域（121）处，以便当将电压施加到第一覆盖栅电极（111）时，改变第一纵向区域（121）中的载流子浓度。 优选地，在第二纵向区域（122）处布置第二覆盖栅电极（112）。 由此可以实现可调谐的人造结（114），而不会明显地掺杂纳米线（105）。

公开(公告)号：US07733174B2

公开(公告)日：2010-06-08

申请号：US12253764

申请日：2008-10-17

Applicant: Arun Kumar Sharma ,  Ryan Erik Lind ,  Ronnie A. Bean

Inventor： Arun Kumar Sharma ,  Ryan Erik Lind ,  Ronnie A. Bean

IPC: H03F1/36

CPC classification number: H03G11/002

Abstract: An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and the amplifier is adapted to receive an audio signal. Each differential amplifier amplifies the difference between an output voltage from the output node with a reference voltages. The FETs are coupled in series with one another between a first and a second voltage, and each FET receives an output from at least one of the differential amplifiers. Additionally, the intermediate node is coupled to a node between at least two FETs.

Abstract translation: 提供了一种装置。 该装置包括放大器，差分放大器和FET。 放大器具有中间节点和输出节点，并且放大器适于接收音频信号。 每个差分放大器放大输出节点的输出电压与参考电压之间的差值。 FET在第一和第二电压之间彼此串联耦合，并且每个FET接收来自至少一个差分放大器的输出。 另外，中间节点耦合到至少两个FET之间的节点。

公开(公告)号：US20090321716A1

公开(公告)日：2009-12-31

申请号：US11922243

申请日：2006-06-16

Applicant: Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

Inventor： Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

IPC: H01L29/12

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/205 ,  H01L29/775

Abstract: A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

Abstract translation: 在具有比Si窄的带隙的半导体材料中实现纳米线缠绕晶体管。 纳米线中的应变弛豫允许将晶体管放置在多种衬底和异质结构中以被并入器件中。 应在晶体管中引入各种类型的异质结，通过减小冲击电离速率，增加电流开/关比，降低子阈值斜率，降低晶体管接触电阻，提高热稳定性，从而降低输出电导。 应通过使用半绝缘基板和在源极和漏极接触区域之间使用横杆几何形状来最小化寄生电容。 晶体管可以在数字高频和低功率电路以及模拟高频电路中使用。

公开(公告)号：US10361284B2

公开(公告)日：2019-07-23

申请号：US15738274

申请日：2016-06-21

Applicant: Lars-Erik Wernersson ,  Johannes Svensson ,  Martin Berg ,  Karl-Magnus Persson ,  Erik Lind

Inventor： Lars-Erik Wernersson ,  Johannes Svensson ,  Martin Berg ,  Karl-Magnus Persson ,  Erik Lind

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/40 ,  H01L29/423 ,  H01L29/739 ,  H01L29/775 ,  H01L29/06

Abstract: A method for fabrication of vertical nanowire MOSFETs is considered using a gate-last process. The top ohmic electrode is first fabricated and may be used as a mask to form a gate recess using etching techniques. The gate is thereafter formed allowing a large degree in access resistance reduction.

公开(公告)号：US20140106553A1

公开(公告)日：2014-04-17

申请号：US14123479

申请日：2012-06-01

Applicant: Mikael Egard ,  Erik Lind ,  Lars-Erik Wernersson

Inventor： Mikael Egard ,  Erik Lind ,  Lars-Erik Wernersson

IPC: H01L21/28

CPC classification number: H01L21/28114 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/845 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66871 ,  H01L29/7787

Abstract: According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.

Abstract translation: 根据本发明构思的一个方面，提供了一种用于制造半导体器件的方法，包括：提供沟道层（104），在沟道层上提供掩模（106），外延生长接触层（108） 与所述沟道层一起在所述接触层上外延生长支撑层（110），其中所述支撑层布置成以比所述接触层更高的速率进行蚀刻，通过移除所述掩模形成延伸穿过所述支撑层的沟槽，以及 在沟槽中提供导体（118）。 还提供了用于制造半导体器件的中间产品。

公开(公告)号：US08551834B2

公开(公告)日：2013-10-08

申请号：US13458310

申请日：2012-04-27

Applicant: Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Lowgren

Inventor： Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Lowgren

IPC: H01L21/76

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7828 ,  H01L29/78642 ,  H01L33/24 ,  Y10S977/888 ,  Y10S977/89

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract translation: 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。

公开(公告)号：US20100102380A1

公开(公告)日：2010-04-29

申请号：US12441223

申请日：2007-09-18

Applicant: Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Löwgren

Inventor： Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Löwgren

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7828 ,  H01L29/78642 ,  H01L33/24 ,  Y10S977/888 ,  Y10S977/89

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilised in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract translation: 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。

公开(公告)号：US20090294757A1

公开(公告)日：2009-12-03

申请号：US11922242

申请日：2006-06-16

Applicant: Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

Inventor： Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

IPC: H01L29/06 ,  H01L23/482 ,  B82B1/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/205 ,  H01L29/775

Abstract: The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved.

Abstract translation: 本发明涉及具有垂直纳米线作为功能部件的纳米级电子器件。 触点设置在纳米线的不同部分的纳米线上，例如漏极和源极触点。 与纳米线接触相关的是外部电极，其连接在不同的水平，如从衬底所看到的那样。 外部电极是细长的，并且通常且优选条纹状。 根据本发明，与纳米线的第一部分处的接触相关联的第一外部电极或触点和与纳米线的第二部分处的接触相关联的第二外部电极被布置成十字形 - 栏配置。 横杆配置使外部电极的覆盖最小化，因此可以减小寄生电容和电流泄漏，并且改善器件的性能。

公开(公告)号：US09087896B2

公开(公告)日：2015-07-21

申请号：US14048502

申请日：2013-10-08

Applicant: Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Lowgren

Inventor： Jonas Ohlsson ,  Lars Samuelson ,  Erik Lind ,  Lars-Erik Wernersson ,  Truls Lowgren

IPC: H01L29/66 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/12 ,  H01L29/775 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L33/24

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7828 ,  H01L29/78642 ,  H01L33/24 ,  Y10S977/888 ,  Y10S977/89

Abstract: The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.

Abstract translation: 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。

公开(公告)号：US20100176459A1

公开(公告)日：2010-07-15

申请号：US12441220

申请日：2007-09-19

Applicant: Lars-Erik Wernersson ,  Erik Lind ,  Tomas Bryllert ,  Jonas Ohlsson ,  Truls Löwgren ,  Lars Samuelson ,  Claes Thelander

Inventor： Lars-Erik Wernersson ,  Erik Lind ,  Tomas Bryllert ,  Jonas Ohlsson ,  Truls Löwgren ,  Lars Samuelson ,  Claes Thelander

IPC: H01L27/088 ,  H01L21/36

CPC classification number: H01L27/0883 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/20 ,  H01L29/775 ,  H01L29/7828

Abstract: The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

Abstract translation: 本发明涉及具有封盖几何形状的垂直纳米线晶体管。 垂直纳米线晶体管的阈值电压由纳米线的直径，纳米线的掺杂，纳米线中的异质结构段的引入，纳米线周围的壳结构中的掺杂来调节，栅极的功函数 堆叠，通过应变工程，通过控制电介质或纳米线材料的选择。 具有不同阈值电压的晶体管设置在相同的基板上，这使得能够利用阈值电压的偏移设计高级电路，类似于直接耦合的场逻辑。