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    Semiconductor Nanowire Transistor
    3.
    发明申请
    Semiconductor Nanowire Transistor 有权
    半导体纳米线晶体管

    公开(公告)号：US20090321716A1

    公开(公告)日：2009-12-31

    申请号：US11922243

    申请日：2006-06-16

    Applicant: Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

    Inventor： Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

    IPC: H01L29/12

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/205 ,  H01L29/775

    Abstract: A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

    Abstract translation: 在具有比Si窄的带隙的半导体材料中实现纳米线缠绕晶体管。 纳米线中的应变弛豫允许将晶体管放置在多种衬底和异质结构中以被并入器件中。 应在晶体管中引入各种类型的异质结，通过减小冲击电离速率，增加电流开/关比，降低子阈值斜率，降低晶体管接触电阻，提高热稳定性，从而降低输出电导。 应通过使用半绝缘基板和在源极和漏极接触区域之间使用横杆几何形状来最小化寄生电容。 晶体管可以在数字高频和低功率电路以及模拟高频电路中使用。

    Semiconductor nanowire vertical device architecture
    6.
    发明授权
    Semiconductor nanowire vertical device architecture 有权
    半导体纳米线垂直器件架构

    公开(公告)号：US08344361B2

    公开(公告)日：2013-01-01

    申请号：US11922242

    申请日：2006-06-16

    Applicant: Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

    Inventor： Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

    IPC: H01L51/00 ,  H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/205 ,  H01L29/775

    Abstract: The present invention relates to nanoscaled electronic devices with a vertical nanowire as a functional part. Contacts are arranged on the nanowire at different parts of the nanowire, for example drain and source contacts. In connection to the nanowire contacts are external electrodes, that connect at different levels, as seen from the substrate, of the device. The external electrodes are elongated, and typically and preferably stripe-like. According to the invention a first external electrode, or contacts, associated with contact(s) at a first part of the nanowire, and a second external electrode, associated with contact(s) at a second part of the nanowire are arranged in a cross-bar configuration. The cross-bar configuration minimizes the overlay of the external electrodes, hence, parasitic capacitances and current leakage can be reduced, and the performance of the device improved.

    Abstract translation: 本发明涉及具有垂直纳米线作为功能部件的纳米级电子器件。 触点设置在纳米线的不同部分的纳米线上，例如漏极和源极触点。 与纳米线接触相关的是外部电极，其连接在不同的水平，如从衬底所看到的那样。 外部电极是细长的，并且通常且优选条纹状。 根据本发明，与纳米线的第一部分处的接触相关联的第一外部电极或触点和与纳米线的第二部分处的接触相关联的第二外部电极被布置成十字形 - 栏配置。 横杆配置使外部电极的覆盖最小化，因此可以减小寄生电容和电流泄漏，并且改善器件的性能。

    Semiconductor nanowire transistor
    7.
    发明授权
    Semiconductor nanowire transistor 有权
    半导体纳米线晶体管

    公开(公告)号：US08330143B2

    公开(公告)日：2012-12-11

    申请号：US11922243

    申请日：2006-06-16

    Applicant: Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

    Inventor： Lars-Erik Wernersson ,  Tomas Bryllert ,  Erik Lind ,  Lars Samuelson

    IPC: H01L29/06 ,  H01L31/00

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/165 ,  H01L29/205 ,  H01L29/775

    Abstract: A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

    Abstract translation: 在具有比Si窄的带隙的半导体材料中实现纳米线缠绕晶体管。 纳米线中的应变弛豫允许将晶体管放置在多种衬底和异质结构中以被并入器件中。 应在晶体管中引入各种类型的异质结，通过减小冲击电离速率，增加电流开/关比，降低子阈值斜率，降低晶体管接触电阻，提高热稳定性，从而降低输出电导。 应通过使用半绝缘基板和在源极和漏极访问区域之间使用横杆几何形状来最小化寄生电容。 晶体管可以在数字高频和低功率电路以及模拟高频电路中使用。

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