公开(公告)号：US20160055004A1

公开(公告)日：2016-02-25

申请号：US14465652

申请日：2014-08-21

Applicant: EDWARD T. GROCHOWSKI ,  MILIND B. GIRKAR ,  VICTOR W. LEE ,  DMITRY M. MASLENNIKOV ,  ROBERT VALENTINE ,  SERGEY A. ROZHKOV ,  BORIS A. BABAYAN

Inventor： EDWARD T. GROCHOWSKI ,  MILIND B. GIRKAR ,  VICTOR W. LEE ,  DMITRY M. MASLENNIKOV ,  ROBERT VALENTINE ,  SERGEY A. ROZHKOV ,  BORIS A. BABAYAN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30094 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/384

Abstract: An apparatus and method are described for non-speculative execution of conditional instructions. For example, one embodiment of a processor comprises: a register set including a first register to store a set of one or more condition bits; non-speculative execution logic to execute a first instruction to identify a first target instruction strand in response to a first conditional value read from the set of condition bits, the first instruction to wait until the first conditional value becomes known before causing the first target instruction strand to be fetched and executed, the non-speculative execution logic to execute a second instruction to identify an end of the first target instruction strand and responsively identify a new current instruction pointer for instructions which follow the second instruction; and out-of-order execution logic to fetch and execute the instructions which follow the second instruction prior to the execution of the second instruction.

Abstract translation: 描述了用于非推测性执行条件指令的装置和方法。 例如，处理器的一个实施例包括：寄存器集合，其包括用于存储一组或多个条件位的第一寄存器; 非推测执行逻辑，用于执行第一指令以响应于从所述条件位集合读取的第一条件值来识别第一目标指令串，所述第一指令等待所述第一条件值在导致所述第一目标指令之前已知 所述非推测执行逻辑执行用于识别所述第一目标指令串的结束的第二指令，并且响应于识别用于所述第二指令之后的指令的新的当前指令指针; 以及无序执行逻辑，以在执行第二指令之前获取和执行遵循第二指令的指令。

公开(公告)号：US20150052333A1

公开(公告)日：2015-02-19

申请号：US14341643

申请日：2014-07-25

Applicant: Christopher J. HUGHES ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Bret TOLL ,  Robert C. VALENTINE ,  Milind B. GIRKAR ,  Andrew T. FORSYTH ,  Edward T. GROCHOWSKI ,  Jonathan C. HALL

Inventor： Christopher J. HUGHES ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Bret TOLL ,  Robert C. VALENTINE ,  Milind B. GIRKAR ,  Andrew T. FORSYTH ,  Edward T. GROCHOWSKI ,  Jonathan C. HALL

IPC: G06F9/30

Abstract: Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask.

Abstract translation: 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，根据写入掩码的位值的至少一些，执行收集步幅指令导致从存储器进入到目的地寄存器的条带数据元素的有条件存储。

公开(公告)号：US20140095831A1

公开(公告)日：2014-04-03

申请号：US13631071

申请日：2012-09-28

Applicant: Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

Inventor： Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/355

Abstract: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

Abstract translation: 描述了一种用于在流水线处理器中执行有效收集操作的装置和方法。 例如，根据本发明的一个实施例的处理器包括：收集设置逻辑，用于在预期一个或多个收集操作中执行一个或多个收集设置操作，所述收集设置操作确定向量数据元素的一个或多个地址 聚集在一起聚集; 并收集逻辑以执行一个或多个收集操作以使用由收集设置操作确定的一个或多个地址来收集向量数据元素。

公开(公告)号：US07380111B2

公开(公告)日：2008-05-27

申请号：US10888052

申请日：2004-07-08

Applicant: Edward T. Grochowski ,  Jared W. Stark

Inventor： Edward T. Grochowski ,  Jared W. Stark

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. The instruction with an incorrectly-predicted predicate is flushed from the pipeline if the predicted value and the architecturally correct value are different.

Abstract translation: 一种用于处理乱序处理器中的寄存器的方法。 预测指令中的谓词。 然后使用读 - 修改 - 写操作来计算结构上正确的值。 将预测值与架构正确的值进行比较。 如果预测值和架构上正确的值不同，则具有错误预测谓词的指令将从流水线中刷新。

公开(公告)号：US07281140B2

公开(公告)日：2007-10-09

申请号：US10041092

申请日：2001-12-28

Applicant: James S. Burns ,  Stefan Rusu ,  David J. Ayers ,  Edward T. Grochowski ,  Marsha Eng ,  Vivek Tiwari

Inventor： James S. Burns ,  Stefan Rusu ,  David J. Ayers ,  Edward T. Grochowski ,  Marsha Eng ,  Vivek Tiwari

IPC: G06F1/04

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F9/3017 ,  G06F9/3873 ,  Y02D10/128 ,  Y02D10/152

Abstract: A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the scaled activity. If the power state reaches a first threshold, the operating point of the processor is adjusted and a new scaling factor is selected to determine the power state.

Abstract translation: 处理器包括数字油门以监视处理器的指令执行流水线的各个单元的活动。 监视的活动根据处理器的当前工作点进行缩放，并且从缩放的活动确定功率状态。 如果功率状态达到第一阈值，则调整处理器的工作点并选择新的比例因子来确定功率状态。

公开(公告)号：US6076153A

公开(公告)日：2000-06-13

申请号：US998341

申请日：1997-12-24

Applicant: Edward T. Grochowski ,  Derrick C. Lin

Inventor： Edward T. Grochowski ,  Derrick C. Lin

IPC: G06F9/38 ,  G06F15/76

CPC classification number: G06F9/3861 ,  G06F9/3842

Abstract: The invention, in one embodiment, is a method for committing the results of at least two speculatively executed instructions to an architectural state in a superscalar processor. The method includes determining which of the speculatively executed instructions encountered a problem in execution, and replaying the instruction that encountered the problem in execution while retaining the results of executing the instruction that did not encounter the problem.

Abstract translation: 在一个实施例中，本发明是一种用于将至少两个推测执行的指令的结果提交到超标量处理器中的架构状态的方法。 该方法包括确定哪些推测执行的指令遇到执行中的问题，并且在保留执行没有遇到该问题的指令的结果的同时重播遇到执行中的问题的指令。

公开(公告)号：US09977674B2

公开(公告)日：2018-05-22

申请号：US10685654

申请日：2003-10-14

Applicant: Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Edward T. Grochowski ,  Bryan P. Black

Inventor： Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Edward T. Grochowski ,  Bryan P. Black

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384

Abstract: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

公开(公告)号：US20160239074A1

公开(公告)日：2016-08-18

申请号：US14621709

申请日：2015-02-13

Applicant: VICTOR W. LEE ,  EDWARD T. GROCHOWSKI ,  DAEHYUN KIM ,  YUXIN BAI ,  SHENG LI ,  NAVEEN K. MELLEMPUDI ,  DHIRAJ D. KALAMKAR

Inventor： VICTOR W. LEE ,  EDWARD T. GROCHOWSKI ,  DAEHYUN KIM ,  YUXIN BAI ,  SHENG LI ,  NAVEEN K. MELLEMPUDI ,  DHIRAJ D. KALAMKAR

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括：多个第一核，用于独立地执行指令，所述多个第一核中的每一个包括存储执行信息的多个计数器; 用于执行存储器操作的至少一个第二核心; 以及功率控制器，用于从所述多个计数器中的至少一些计数器接收性能信息，至少部分地基于所述性能信息确定在所述处理器上执行的工作负载类型，并且基于所述工作负载类型，动态地从一个或多个计算机迁移一个或多个线程 或多个第一核心到至少一个第二核心，以在下一个操作间隔期间执行。 描述和要求保护其他实施例。

公开(公告)号：US08533436B2

公开(公告)日：2013-09-10

申请号：US12492652

申请日：2009-06-26

Applicant: Joshua B. Fryman ,  Edward T. Grochowski ,  Toni Juan ,  Andrew Thomas Forsyth ,  John Mejia ,  Ramacharan Sundararaman ,  Eric Sprangle ,  Roger Espasa ,  Ravi Rajwar

Inventor： Joshua B. Fryman ,  Edward T. Grochowski ,  Toni Juan ,  Andrew Thomas Forsyth ,  John Mejia ,  Ramacharan Sundararaman ,  Eric Sprangle ,  Roger Espasa ,  Ravi Rajwar

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F9/30185 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0817

Abstract: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。

公开(公告)号：US07516312B2

公开(公告)日：2009-04-07

申请号：US10817263

申请日：2004-04-02

Applicant: Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

Inventor： Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

IPC: G06F15/00 ,  G06F9/00

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/3848

Abstract: An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

Abstract translation: 指令预取装置包括分支目标缓冲器（BTB），远视目标缓冲器（PTB）和预取流缓冲器（PSB）。 BTB包括将分支地址映射到分支目标地址的记录，PTB包括将分支目标地址映射到后续分支目标地址的记录。 当遇到分支指令时，BTB可以将动态相邻的后续块条目位置预测为记录中还包括分支指令地址的分支目标地址。 PTB可以通过将分支目标地址映射到后续动态块来预测多个后续块。 PSB保存由PTB预测的后续块预取的指令。