公开(公告)号：US09785442B2

公开(公告)日：2017-10-10

申请号：US14582897

申请日：2014-12-24

Applicant: Elmoustapha Ould-Ahmed-Vall ,  Christopher J. Hughes ,  Robert Valentine ,  Milind B. Girkar

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Christopher J. Hughes ,  Robert Valentine ,  Milind B. Girkar

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/46

CPC classification number: G06F9/3016 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/34 ,  G06F9/3455 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/467

Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address and an operand to store a stride value, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

公开(公告)号：US20160188342A1

公开(公告)日：2016-06-30

申请号：US14582791

申请日：2014-12-24

Applicant: Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

Inventor： Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30007 ,  G06F9/30101 ,  G06F9/3861

Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode, and execution hardware to execute the decoded instruction inside a speculative execution (DSX) and rollback execution to a stored address and clear a DSX status indication in a DSX status register, and thereby abort the DSX.

Abstract translation: 描述用于数据推测执行（DSX）的系统，方法和装置。 在一些实施例中，用于执行DSX的硬件设备包括硬件解码器，用于对指令进行解码，包括操作码的指令和执行硬件，以在推测执行（DSX）内执行解码的指令，并将回滚执行回滚到存储的地址并清除 DSX状态寄存器中的DSX状态指示，从而中止DSX。

公开(公告)号：US20160188328A1

公开(公告)日：2016-06-30

申请号：US14582776

申请日：2014-12-24

Applicant: Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

Inventor： Elmoustapha OULD-AHMED-VALL ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Milind B. GIRKAR

IPC: G06F9/30 ,  G06F9/34

CPC classification number: G06F9/3016 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/467

Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode, and execution hardware to execute the decoded instruction to reset data speculative execution (DSX) tracking hardware to track speculative memory accesses, clear a DSX status indication in a DSX status register, and commit all speculatively executed stores of the DSX region and thereby end a DSX region.

Abstract translation: 描述用于数据推测执行（DSX）的系统，方法和装置。 在一些实施例中，用于执行DSX的硬件装置包括用于解码指令的硬件解码器，包括操作码的指令和执行硬件，以执行解码指令以复位数据推测执行（DSX）跟踪硬件以跟踪推测性存储器访问， 在DSX状态寄存器中清除DSX状态指示，并提交DSX区域的所有推测执行的存储，从而结束一个DSX区域。

公开(公告)号：US08972698B2

公开(公告)日：2015-03-03

申请号：US12976616

申请日：2010-12-22

Applicant: Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

Inventor： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3838

Abstract: A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

Abstract translation: 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

公开(公告)号：US08607235B2

公开(公告)日：2013-12-10

申请号：US11027445

申请日：2004-12-30

Applicant: Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

Inventor： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC: G06F9/46

CPC classification number: G06F9/4843

Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。

公开(公告)号：US20160055004A1

公开(公告)日：2016-02-25

申请号：US14465652

申请日：2014-08-21

Applicant: EDWARD T. GROCHOWSKI ,  MILIND B. GIRKAR ,  VICTOR W. LEE ,  DMITRY M. MASLENNIKOV ,  ROBERT VALENTINE ,  SERGEY A. ROZHKOV ,  BORIS A. BABAYAN

Inventor： EDWARD T. GROCHOWSKI ,  MILIND B. GIRKAR ,  VICTOR W. LEE ,  DMITRY M. MASLENNIKOV ,  ROBERT VALENTINE ,  SERGEY A. ROZHKOV ,  BORIS A. BABAYAN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30094 ,  G06F9/3005 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/384

Abstract: An apparatus and method are described for non-speculative execution of conditional instructions. For example, one embodiment of a processor comprises: a register set including a first register to store a set of one or more condition bits; non-speculative execution logic to execute a first instruction to identify a first target instruction strand in response to a first conditional value read from the set of condition bits, the first instruction to wait until the first conditional value becomes known before causing the first target instruction strand to be fetched and executed, the non-speculative execution logic to execute a second instruction to identify an end of the first target instruction strand and responsively identify a new current instruction pointer for instructions which follow the second instruction; and out-of-order execution logic to fetch and execute the instructions which follow the second instruction prior to the execution of the second instruction.

Abstract translation: 描述了用于非推测性执行条件指令的装置和方法。 例如，处理器的一个实施例包括：寄存器集合，其包括用于存储一组或多个条件位的第一寄存器; 非推测执行逻辑，用于执行第一指令以响应于从所述条件位集合读取的第一条件值来识别第一目标指令串，所述第一指令等待所述第一条件值在导致所述第一目标指令之前已知 所述非推测执行逻辑执行用于识别所述第一目标指令串的结束的第二指令，并且响应于识别用于所述第二指令之后的指令的新的当前指令指针; 以及无序执行逻辑，以在执行第二指令之前获取和执行遵循第二指令的指令。

公开(公告)号：US20150052333A1

公开(公告)日：2015-02-19

申请号：US14341643

申请日：2014-07-25

Applicant: Christopher J. HUGHES ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Bret TOLL ,  Robert C. VALENTINE ,  Milind B. GIRKAR ,  Andrew T. FORSYTH ,  Edward T. GROCHOWSKI ,  Jonathan C. HALL

Inventor： Christopher J. HUGHES ,  Jesus Corbal SAN ADRIAN ,  Roger Espasa SANS ,  Bret TOLL ,  Robert C. VALENTINE ,  Milind B. GIRKAR ,  Andrew T. FORSYTH ,  Edward T. GROCHOWSKI ,  Jonathan C. HALL

IPC: G06F9/30

Abstract: Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask.

Abstract translation: 描述了用于在计算机处理器中执行收集和散播步幅指令的系统，装置和方法的实施例。 在一些实施例中，根据写入掩码的位值的至少一些，执行收集步幅指令导致从存储器进入到目的地寄存器的条带数据元素的有条件存储。

公开(公告)号：US20140344553A1

公开(公告)日：2014-11-20

申请号：US13898189

申请日：2013-05-20

Applicant: Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

Abstract translation: 根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

公开(公告)号：US20140149802A1

公开(公告)日：2014-05-29

申请号：US13688544

申请日：2012-11-29

Applicant: Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

Inventor： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

IPC: G06F11/00

CPC classification number: G06F11/004 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3865 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

Abstract: A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

Abstract translation: 处理器包括执行单元，耦合到执行单元的故障掩模以及耦合到执行单元的抑制掩模。 故障掩码是存储第一多个比特值以指示多元素向量的哪些元素具有响应于在执行单元中的元素上的指令的执行而产生的相关联的故障。 抑制掩模是存储第二多个位值，以指示哪个元件将被抑制相关联的故障。 所述处理器还包括计数器逻辑，以响应于与所述第一元件相关联并从所述故障掩模接收到的第一故障的指示来增加计数器，以及与所述第一元件相关联并从所述抑制掩码接收到的第一抑制的指示。 其他实施例被描述为所要求保护的。

公开(公告)号：US20140115594A1

公开(公告)日：2014-04-24

申请号：US14067223

申请日：2013-10-30

Applicant: Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

Inventor： Richard A. Hankins ,  Hong Wang ,  Gautham N. Chinya ,  Trung A. Diep ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Asit K. Mallick ,  Baiju V. Patel ,  James Paul Held ,  Milind B. Girkar ,  Prashant Sethi ,  Xinmin Tian

IPC: G06F9/48

CPC classification number: G06F9/4843

Abstract: Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例来调度不依赖于操作系统的OS无关的“碎片”。 对于至少一个实施例，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的顺控程序上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。