公开(公告)号：US08996845B2

公开(公告)日：2015-03-31

申请号：US12644529

申请日：2009-12-22

Applicant: Ravi Rajwar ,  Andrew T. Forsyth

Inventor： Ravi Rajwar ,  Andrew T. Forsyth

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30

CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30087

Abstract: A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.

Abstract translation: 通过以下操作来执行向量比较和交换操作：通过处理设备中的解码器进行解码，指定在第一存储位置，第二存储位置和第二存储位置之间的多个数据元素的向量比较和交换操作的单个指令， 和第三存储位置; 发出由处理装置中的执行单元执行的单个指令; 并且响应于所述单个指令的执行，将来自所述第一存储位置的数据元素与所述第二存储位置中的相应数据元素进行比较; 并且响应于确定匹配存在，用来自第三存储位置的相应数据元素从第一存储位置替换数据元素。

公开(公告)号：US08972698B2

公开(公告)日：2015-03-03

申请号：US12976616

申请日：2010-12-22

Applicant: Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

Inventor： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3838

Abstract: A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

Abstract translation: 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

公开(公告)号：US20140173203A1

公开(公告)日：2014-06-19

申请号：US13717981

申请日：2012-12-18

Applicant: Andrew T. Forsyth

Inventor： Andrew T. Forsyth

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/3877 ,  G06F12/0804 ,  G06F12/0891 ,  Y02D10/13

Abstract: In an embodiment, a processor is disclosed and includes a cache memory and a memory execution cluster coupled to the cache memory. The memory execution cluster includes a memory execution unit to execute instructions including non-block memory instructions, and block memory logic to execute one or more block memory operations. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，公开了处理器，并且包括高速缓存存储器和耦合到高速缓冲存储器的存储器执行集群。 存储器执行集群包括执行包括非块存储器指令的指令的存储器执行单元和用于执行一个或多个块存储器操作的块存储器逻辑。 描述和要求保护其他实施例。

公开(公告)号：US20140164705A1

公开(公告)日：2014-06-12

申请号：US13976429

申请日：2011-12-22

Applicant: Jesus Corbal ,  Lisa K. Wu ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Ramacharan Sundararaman

Inventor： Jesus Corbal ,  Lisa K. Wu ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Ramacharan Sundararaman

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/30047 ,  G06F12/0811 ,  G06F12/0862

Abstract: A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.

Abstract translation: 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。

公开(公告)号：US20140149651A1

公开(公告)日：2014-05-29

申请号：US13685991

申请日：2012-11-27

Applicant: Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Mark C. Davis ,  Edward T. Grochowski ,  Robert D. Cavin

Inventor： Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Mark C. Davis ,  Edward T. Grochowski ,  Robert D. Cavin

IPC: G06F12/08

CPC classification number: G06F12/126 ,  G06F12/123 ,  Y02D10/13

Abstract: In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。

公开(公告)号：US20140095779A1

公开(公告)日：2014-04-03

申请号：US13631378

申请日：2012-09-28

Applicant: Andrew T. Forsyth ,  Dennis R. Bradford ,  Jonathan C. Hall

Inventor： Andrew T. Forsyth ,  Dennis R. Bradford ,  Jonathan C. Hall

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/00 ,  G06F3/06 ,  G06F3/0608 ,  G06F3/0641 ,  G06F9/30 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F11/1453 ,  G06F12/0246

Abstract: A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask.

Abstract translation: 一方面的方法包括接收指示第一源打包存储器索引的指令，第二源打包数据操作掩码和目的地存储位置。 将打包的内存索引的内存索引彼此进行比较。 识别一组或多组重复的内存索引。 与每组重复存储器索引对应的数据仅加载一次。 对于集合中的每个重复存储器索引，复制对应于每组重复存储器索引的加载数据。 打包数据导致响应于该指令的目的地存储位置。 打包数据结果包括来自存储器位置的数据元素，当不被打包数据操作掩码的相应元素阻塞时，由打包的存储器索引的相应存储器索引指示。

公开(公告)号：US08539206B2

公开(公告)日：2013-09-17

申请号：US12890571

申请日：2010-09-24

Applicant: Andrew T. Forsyth

Inventor： Andrew T. Forsyth

IPC: G06F9/305

CPC classification number: G06F9/30167 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/34

Abstract: An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands to generate an index value, the index value identifying a subset of bits within an immediate value transmitted with an instruction; reading the bits from the immediate value; and storing the bits read from the immediate value within a destination register to generate a result of the instruction.

Abstract translation: 描述了用于执行由表指定的任意逻辑操作的装置和方法。 例如，用于在计算机处理器上执行逻辑操作的方法的一个实施例包括：从两个或更多个源操作数中的每一个读取数据; 组合从源操作数读取的数据以生成索引值，所述索引值标识用指令发送的立即值内的位的子集; 从立即值读取位; 以及将从立即值读取的比特存储在目的地寄存器中，以生成该指令的结果。

公开(公告)号：US20120166761A1

公开(公告)日：2012-06-28

申请号：US12976616

申请日：2010-12-22

Applicant: Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

Inventor： Christopher J. Hughes ,  Mark J. Charney ,  Yen-Kuang Chen ,  Jesus Corbal ,  Andrew T. Forsyth ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki Ido ,  Robert Valentine ,  Jeffrey Wiedemeier

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3838

Abstract: A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

Abstract translation: 描述了在半导体芯片上实现的处理核心，其具有包括第一比较电路的第一执行单元逻辑电路，以将第一输入向量中的每个元素与第二输入向量的每个元素进行比较。 处理核心还具有第二执行逻辑电路，其包括第二比较电路，用于将第一输入值与输入向量的每个数据元素进行比较。

公开(公告)号：US20120144089A1

公开(公告)日：2012-06-07

申请号：US13250223

申请日：2011-09-30

Applicant: Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

Inventor： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

IPC: G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/345 ,  G06F12/06 ,  G06F12/08

Abstract: Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

Abstract translation: 公开了用于访问用于散射/收集操作的多条数据高速缓存行的方法和装置。 设备的实施例可以包括地址生成逻辑，用于从具有第一值的一组对应的掩码元素中的每一个的索引集合的索引生成地址。 线或库匹配排序逻辑匹配相同高速缓存行或不同库中的地址，并且订购访问序列以允许多个高速缓存行和不同存储体中的一组地址。 地址选择逻辑将地址组指向高速缓存中的对应的不同存储体，以访问与单个访问周期中的地址组对应的多个高速缓存行中的数据元素。 拆卸/重组缓冲器根据其各自的存储体/寄存器位置对数据元素进行排序，并且收集/散布有限状态机将相应的掩模元素的值从第一值改变为第二值。

公开(公告)号：US10157061B2

公开(公告)日：2018-12-18

申请号：US13994060

申请日：2011-12-22

Applicant: Jesus Corbal ,  Matthew J. Craighead ,  Bret L. Toll ,  Andrew T. Forsyth

Inventor： Jesus Corbal ,  Matthew J. Craighead ,  Bret L. Toll ,  Andrew T. Forsyth

IPC: G06F9/30

Abstract: According to one embodiment, an occurrence of an instruction is fetched. The instruction's format specifies its only source operand from a single vector write mask register, and specifies as its destination a single general purpose register. In addition, the instruction's format includes a first field whose contents selects the single vector write mask register, and includes a second field whose contents selects the single general purpose register. The source operand is a write mask including a plurality of one bit vector write mask elements that correspond to different multi-bit data element positions within architectural vector registers. The method also includes, responsive to executing the single occurrence of the single instruction, storing data in the single general purpose register such that its contents represent either a first or second scalar constant based on whether the plurality of one bit vector write mask elements in the source operand are all zero.