公开(公告)号：US07380111B2

公开(公告)日：2008-05-27

申请号：US10888052

申请日：2004-07-08

Applicant: Edward T. Grochowski ,  Jared W. Stark

Inventor： Edward T. Grochowski ,  Jared W. Stark

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. The instruction with an incorrectly-predicted predicate is flushed from the pipeline if the predicted value and the architecturally correct value are different.

Abstract translation: 一种用于处理乱序处理器中的寄存器的方法。 预测指令中的谓词。 然后使用读 - 修改 - 写操作来计算结构上正确的值。 将预测值与架构正确的值进行比较。 如果预测值和架构上正确的值不同，则具有错误预测谓词的指令将从流水线中刷新。

公开(公告)号：US20140095831A1

公开(公告)日：2014-04-03

申请号：US13631071

申请日：2012-09-28

Applicant: Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

Inventor： Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/355

Abstract: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

Abstract translation: 描述了一种用于在流水线处理器中执行有效收集操作的装置和方法。 例如，根据本发明的一个实施例的处理器包括：收集设置逻辑，用于在预期一个或多个收集操作中执行一个或多个收集设置操作，所述收集设置操作确定向量数据元素的一个或多个地址 聚集在一起聚集; 并收集逻辑以执行一个或多个收集操作以使用由收集设置操作确定的一个或多个地址来收集向量数据元素。

公开(公告)号：US07281140B2

公开(公告)日：2007-10-09

申请号：US10041092

申请日：2001-12-28

Applicant: James S. Burns ,  Stefan Rusu ,  David J. Ayers ,  Edward T. Grochowski ,  Marsha Eng ,  Vivek Tiwari

Inventor： James S. Burns ,  Stefan Rusu ,  David J. Ayers ,  Edward T. Grochowski ,  Marsha Eng ,  Vivek Tiwari

IPC: G06F1/04

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/3243 ,  G06F9/3017 ,  G06F9/3873 ,  Y02D10/128 ,  Y02D10/152

Abstract: A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the scaled activity. If the power state reaches a first threshold, the operating point of the processor is adjusted and a new scaling factor is selected to determine the power state.

Abstract translation: 处理器包括数字油门以监视处理器的指令执行流水线的各个单元的活动。 监视的活动根据处理器的当前工作点进行缩放，并且从缩放的活动确定功率状态。 如果功率状态达到第一阈值，则调整处理器的工作点并选择新的比例因子来确定功率状态。

公开(公告)号：US6076153A

公开(公告)日：2000-06-13

申请号：US998341

申请日：1997-12-24

Applicant: Edward T. Grochowski ,  Derrick C. Lin

Inventor： Edward T. Grochowski ,  Derrick C. Lin

IPC: G06F9/38 ,  G06F15/76

CPC classification number: G06F9/3861 ,  G06F9/3842

Abstract: The invention, in one embodiment, is a method for committing the results of at least two speculatively executed instructions to an architectural state in a superscalar processor. The method includes determining which of the speculatively executed instructions encountered a problem in execution, and replaying the instruction that encountered the problem in execution while retaining the results of executing the instruction that did not encounter the problem.

Abstract translation: 在一个实施例中，本发明是一种用于将至少两个推测执行的指令的结果提交到超标量处理器中的架构状态的方法。 该方法包括确定哪些推测执行的指令遇到执行中的问题，并且在保留执行没有遇到该问题的指令的结果的同时重播遇到执行中的问题的指令。

公开(公告)号：US09977674B2

公开(公告)日：2018-05-22

申请号：US10685654

申请日：2003-10-14

Applicant: Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Edward T. Grochowski ,  Bryan P. Black

Inventor： Jeffrey P. Rupley, II ,  Edward A. Brekelbaum ,  Edward T. Grochowski ,  Bryan P. Black

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384

Abstract: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

公开(公告)号：US08533436B2

公开(公告)日：2013-09-10

申请号：US12492652

申请日：2009-06-26

Applicant: Joshua B. Fryman ,  Edward T. Grochowski ,  Toni Juan ,  Andrew Thomas Forsyth ,  John Mejia ,  Ramacharan Sundararaman ,  Eric Sprangle ,  Roger Espasa ,  Ravi Rajwar

Inventor： Joshua B. Fryman ,  Edward T. Grochowski ,  Toni Juan ,  Andrew Thomas Forsyth ,  John Mejia ,  Ramacharan Sundararaman ,  Eric Sprangle ,  Roger Espasa ,  Ravi Rajwar

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40

CPC classification number: G06F9/30185 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0817

Abstract: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。

公开(公告)号：US07516312B2

公开(公告)日：2009-04-07

申请号：US10817263

申请日：2004-04-02

Applicant: Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

Inventor： Hong Wang ,  Ralph Kling ,  Edward T. Grochowski ,  Kalpana Ramakrishnan

IPC: G06F15/00 ,  G06F9/00

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/3848

Abstract: An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent branch target addresses. When a branch instruction is encountered, the BTB can predict the dynamically adjacent subsequent block entry location as the branch target address in the record that also includes the branch instruction address. The PTB can predict multiple subsequent blocks by mapping the branch target address to subsequent dynamic blocks. The PSB holds instructions prefetched from subsequent blocks predicted by the PTB.

Abstract translation: 指令预取装置包括分支目标缓冲器（BTB），远视目标缓冲器（PTB）和预取流缓冲器（PSB）。 BTB包括将分支地址映射到分支目标地址的记录，PTB包括将分支目标地址映射到后续分支目标地址的记录。 当遇到分支指令时，BTB可以将动态相邻的后续块条目位置预测为记录中还包括分支指令地址的分支目标地址。 PTB可以通过将分支目标地址映射到后续动态块来预测多个后续块。 PSB保存由PTB预测的后续块预取的指令。

公开(公告)号：US07111154B2

公开(公告)日：2006-09-19

申请号：US10606511

申请日：2003-06-25

Applicant: Jeffrey P. Rupley ,  Edward A. Brekelbaum ,  Edward T. Grochowski

Inventor： Jeffrey P. Rupley ,  Edward A. Brekelbaum ,  Edward T. Grochowski

IPC: G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

Abstract: Embodiments of an apparatus, method, and system provide for no-operation instruction (“NOP”) folding such that information regarding the presence of a NOP instruction in the instruction stream is folded into a buffer entry for another instruction. Information regarding a target NOP instruction is thus maintained in a buffer entry associated with an instruction other than the target NOP instruction. For at least one embodiment, NOP information is folded into entries of a re-order buffer.

Abstract translation: 装置，方法和系统的实施例提供无操作指令（“NOP”）折叠，使得关于在指令流中存在NOP指令的信息被折叠成用于另一指令的缓冲器条目。 因此，关于目标NOP指令的信息保持在与除了目标NOP指令之外的指令相关联的缓冲器条目中。 对于至少一个实施例，NOP信息被折叠成重新排序缓冲器的条目。

公开(公告)号：US06757814B2

公开(公告)日：2004-06-29

申请号：US10082499

申请日：2002-02-22

Applicant: Ralph M. Kling ,  Edward T. Grochowski ,  Hans J. Mulder

Inventor： Ralph M. Kling ,  Edward T. Grochowski ,  Hans J. Mulder

IPC: G06F938

CPC classification number: G06F9/30094 ,  G06F9/30072 ,  G06F9/3844 ,  G06F9/3861

Abstract: A method and apparatus for performing predicate prediction. In one method, both a predicted predicate value for a predicate and a confidence value for the predicted predicate value are determined.

Abstract translation: 一种执行谓词预测的方法和装置。 在一种方法中，确定预测谓词值的预测谓词值和预测谓词值的置信度值。

公开(公告)号：US06615366B1

公开(公告)日：2003-09-02

申请号：US09470096

申请日：1999-12-21

Applicant: Edward T. Grochowski ,  William Rash ,  Nhon Quach ,  Hang Nguyen ,  Andres Rabago

Inventor： Edward T. Grochowski ,  William Rash ,  Nhon Quach ,  Hang Nguyen ,  Andres Rabago

IPC: G06F1100

CPC classification number: G06F11/1641 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885 ,  G06F2201/845

Abstract: A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to the type of code segment to be executed. When the processor is in high performance mode, the dual execution cores operate in lock step on identical instructions, and the execution results generated by each execution core are compared to detect any errors. In high performance monde, the dual execution cores operate independently.

Abstract translation: 根据要执行的代码段的类型，提供具有可以在高可靠性和高性能执行模式之间切换的双执行核的处理器。 当处理器处于高性能模式时，双执行核心以相同的指令执行锁定步骤，​​并对每个执行核心产生的执行结果进行比较，以检测任何错误。 在高性能的世界，双执行核心独立运行。