公开(公告)号：US20110095359A1

公开(公告)日：2011-04-28

申请号：US12824075

申请日：2010-06-25

Applicant: Naveen Tipirneni ,  Deva N. Pattanayak

Inventor： Naveen Tipirneni ,  Deva N. Pattanayak

IPC: H01L27/088

CPC classification number: H01L29/7813 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66734

Abstract: A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.

Abstract translation: 沟槽金属氧化物半导体场效应晶体管（TMOSFET）包括设置在多个栅极区域之间的多个台面。 每个台面包括漂移区域和身体区域。 台面的宽度在栅极绝缘体区域和体区域之间的界面处是量子阱尺寸的量级。TMOSFET还包括设置在栅极区域与体区域之间的多个栅极绝缘体区域，漂移区域和漏极 地区。 栅极区域和漏极区域之间的栅极绝缘体区域的厚度导致处于OFF状态的栅极 - 漏极电场，其基本上横向有助于消除漂移区域中的电荷。

公开(公告)号：US07833863B1

公开(公告)日：2010-11-16

申请号：US12107738

申请日：2008-04-22

Applicant: Deva N Pattanayak ,  Robert Xu

Inventor： Deva N Pattanayak ,  Robert Xu

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/1095

Abstract: Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.

Abstract translation: 本发明的实施例提供了一种改进的闭孔沟槽金属氧化物半导体场效应晶体管（TMOSFET）。 闭孔TMOSFET包括漏极，设置在漏极区域上方的体区，设置在体区中的栅极区，栅极绝缘体区，多个源极区，设置在靠近该区的外围的身体区域的表面 栅极绝缘体区域。 栅极区域和栅极氧化物区域的第一部分形成为平行细长结构。 栅极区域和氧化物区域的第二部分形成为平行 - 平行的细长结构。 栅极和漏极重叠区域的一部分被身体区域选择性地阻挡，导致较低的整体栅极 - 漏极电容。

公开(公告)号：US20080258212A1

公开(公告)日：2008-10-23

申请号：US12098950

申请日：2008-04-07

Applicant: Deva N. Pattanayak ,  Kyle Terrill ,  Sharon Shi ,  Misha Lee ,  Yuming Bai ,  Kam Lui ,  Kuo-In Chen

Inventor： Deva N. Pattanayak ,  Kyle Terrill ,  Sharon Shi ,  Misha Lee ,  Yuming Bai ,  Kam Lui ,  Kuo-In Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/0727 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66143 ,  H01L29/66477 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

Abstract translation: 与沟槽金属氧化物半导体（MOS）势垒肖特基（TMBS）器件的多晶硅区域以及MOS场效应晶体管（MOSFET）部分的多晶硅区域和单片集成TMBS中的TMBS部分的远程触点和 MOSFET（SKYFET）器件。 多晶硅相对于相邻的台面凹陷。 源极金属与TMBS部分的多晶硅区域的接触是通过将多晶硅延伸到TMBS部分的有源区域之外来实现的。 器件结构的这种改变减轻了在接触步骤之前从TMBS部分的多晶硅和硅台面区域中去除所有氧化物的需要。 因此，避免了接触金属侵入到TMBS器件或SKYFET器件中的沟槽的侧壁中。

公开(公告)号：US4980740A

公开(公告)日：1990-12-25

申请号：US329034

申请日：1989-03-27

Applicant: Deva N. Pattanayak ,  Bantval J. Baliga

Inventor： Deva N. Pattanayak ,  Bantval J. Baliga

IPC: H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L29/7395

Abstract: A MOS-pilot structure for an IGT device consisting of a multiplicity of IGT cells interconnected in a lattice network includes a plurality of pilot emitter electrodes each in electrical contact with only at least one pilot emitter region of a first plurality of the multiplicity of IGT cells and electrically isolated from a common cathode electrode of the multiplicity of IGT cells. The plurality of pilot emitter electrodes are each electrically connected to a contact metal strip deposited on the substrate surface and spaced therefrom by a layer of insulation. The contact metal strip is connected to ground potential through a sense resistor for producing a sense voltage responsive only to the channel currents flowing through the at least one pilot emitter regions; therefore, a MOS pilot structure that utilizes only the MOS channel current to produce the sense voltage to cause turn-off of the IGT device at a large total current is disclosed. The MOS-pilot structure does not suffer from the avalanche breakdown problems during turn-off, that are associated with other prior art IGT pilot structures.

公开(公告)号：US20110049682A1

公开(公告)日：2011-03-03

申请号：US12873147

申请日：2010-08-31

Applicant: Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

Inventor： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC: H01L29/06 ,  H01L21/203 ,  H01L21/302

CPC classification number: H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Abstract translation: 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：US07279743B2

公开(公告)日：2007-10-09

申请号：US10726922

申请日：2003-12-02

Applicant: Deva N. Pattanayak ,  Robert Xu

Inventor： Deva N. Pattanayak ,  Robert Xu

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/1095

Abstract: Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.

Abstract translation: 本发明的实施例提供了一种改进的闭孔沟槽金属氧化物半导体场效应晶体管（TMOSFET）。 闭孔TMOSFET包括漏极，设置在漏极区域上方的体区，设置在体区中的栅极区，栅极绝缘体区，多个源极区，设置在靠近该区的外围的本体区的表面 栅极绝缘体区域。 栅极区域和栅极氧化物区域的第一部分形成为平行细长结构。 栅极区域和氧化物区域的第二部分形成为平行 - 平行的细长结构。 栅极和漏极重叠区域的一部分被主体区域选择性地阻挡，导致较低的整体栅极 - 漏极电容。

公开(公告)号：US07233043B2

公开(公告)日：2007-06-19

申请号：US11150016

申请日：2005-06-10

Applicant: Deva N. Pattanayak

Inventor： Deva N. Pattanayak

IPC: H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734

Abstract: A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.

Abstract translation: 沟槽栅MOSFET包括形成在沟槽的相对侧上的相邻台面。 第一台面中的主体区域向下延伸到沟槽的水平面以下且横向穿过沟槽的底部。 第二台面中的主体区域沿台面的一部分延伸，留下一部分排水口邻接沟槽。 第二台面中的主体区域包括与沟槽的壁相邻的沟道区域。 因此，漏极邻接沟槽的区域相对受限，并且器件的漏极 - 栅极电容减小。 此外，漏极 - 栅极电容取决于沟槽的深度和宽度，允许更大的MOSFET设计自由度。

公开(公告)号：US07183610B2

公开(公告)日：2007-02-27

申请号：US10836833

申请日：2004-04-30

Applicant: Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

Inventor： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

IPC: H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract translation: 在沟槽MOSFET中，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。

公开(公告)号：US06903412B2

公开(公告)日：2005-06-07

申请号：US10106812

申请日：2002-03-26

Applicant: Mohamed N. Darwish ,  Christiana Yue ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill ,  Deva N. Pattanayak

Inventor： Mohamed N. Darwish ,  Christiana Yue ,  Frederick P. Giles ,  Kam Hong Lui ,  Kuo-In Chen ,  Kyle Terrill ,  Deva N. Pattanayak

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66621 ,  H01L29/7834

Abstract: The gate oxide layer of a trench MIS device includes a graduated transition region, where the thickness of the gate oxide layer decreases gradually from a thick section adjacent the bottom of the trench to a thin section adjacent the sidewall of the trench. The PN junction between the body and drain regions intersects the trench in the transition region. This structure allows for a greater margin of error in the placement of the PN junction during the manufacture of the device, since the intersection between the PN junction can be located anywhere in the transition region. The MIS device also has improved breakdown characteristics.

Abstract translation: 沟槽MIS器件的栅极氧化层包括刻蚀过渡区域，其中栅极氧化物层的厚度从邻近沟槽底部的厚部分逐渐减小到邻近沟槽侧壁的薄部分。 体区和漏区之间的PN结与过渡区中的沟槽相交。 这种结构允许在器件制造期间在PN结的放置方面具有更大的误差余量，因为PN结的交点可位于过渡区域的任何地方。 MIS器件还具有改善的击穿特性。

公开(公告)号：US09842911B2

公开(公告)日：2017-12-12

申请号：US13484114

申请日：2012-05-30

Applicant: Naveen Tipirneni ,  Deva N. Pattanayak

Inventor： Naveen Tipirneni ,  Deva N. Pattanayak

IPC: H01L31/119 ,  H01L29/66 ,  H01L21/266 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/66712 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7811

Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.