公开(公告)号：US09443974B2

公开(公告)日：2016-09-13

申请号：US12549190

申请日：2009-08-27

Applicant: Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

Inventor： Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Abstract translation: 描述了制造超结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件的方法。 超级结中的p型掺杂剂的列通过第一列氧化物与第一列n型掺杂剂与第二列氧化物与第二列n型掺杂剂分离。 在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂的列上; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列之上。

公开(公告)号：US09431530B2

公开(公告)日：2016-08-30

申请号：US12788158

申请日：2010-05-26

Applicant: Robert Q. Xu ,  Kuo-In Chen ,  Karl Lichtenberger ,  Sharon Shi ,  Qufei Chen ,  Kyle Terrill

Inventor： Robert Q. Xu ,  Kuo-In Chen ,  Karl Lichtenberger ,  Sharon Shi ,  Qufei Chen ,  Kyle Terrill

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0638 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7811

Abstract: A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.

Abstract translation: 在一个实施例中，一种方法可以包括在垂直金属氧化物半导体场效应晶体管（MOSFET）的主体区域中形成多个沟槽。 此外，该方法可以包括将角度注入源区域进入体区域。 此外，电介质材料可以在多个沟槽内生长。 栅极多晶硅可以沉积在多个沟槽内。 此外，该方法可以包括化学机械抛光栅极多晶硅。 该方法还可以包括蚀刻多个沟槽内的栅极多晶硅。

公开(公告)号：US09425306B2

公开(公告)日：2016-08-23

申请号：US12548841

申请日：2009-08-27

Applicant: Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

Inventor： Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Abstract translation: 在超结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件中，超结中的p型掺杂剂列由第一列氧化物和第二列与第一列n型掺杂剂分离， 的n型掺杂剂通过第二列氧化物。 在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂的列上; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列之上。

公开(公告)号：US20160225622A1

公开(公告)日：2016-08-04

申请号：US14988639

申请日：2016-01-05

Applicant: Hamilton LU ,  The-Tu CHAU ,  Kyle TERRILL ,  Deva N. PATTANAYAK ,  Sharon SHI ,  Kuo-In CHEN ,  Robert XU

Inventor： Hamilton LU ,  The-Tu CHAU ,  Kyle TERRILL ,  Deva N. PATTANAYAK ,  Sharon SHI ,  Kuo-In CHEN ,  Robert XU

IPC: H01L21/02 ,  H01L29/36 ,  H01L29/16

CPC classification number: H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Abstract translation: 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：US20110049614A1

公开(公告)日：2011-03-03

申请号：US12548841

申请日：2009-08-27

Applicant: Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

Inventor： Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Abstract translation: 在超结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件中，超结中的p型掺杂剂列由第一列氧化物和第二列与第一列n型掺杂剂分离， 的n型掺杂剂通过第二列氧化物。 在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂的列上; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列之上。

公开(公告)号：US20100019316A1

公开(公告)日：2010-01-28

申请号：US12586906

申请日：2009-09-29

Applicant: Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

Inventor： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: A method of fabricating a trench MOSFET, the lower portion of the trench containing a buried source electrode which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract translation: 一种制造沟槽MOSFET的方法，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。

公开(公告)号：US07557409B2

公开(公告)日：2009-07-07

申请号：US11698519

申请日：2007-01-26

Applicant: Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

Inventor： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

IPC: H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract translation: 在沟槽MOSFET中，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。

公开(公告)号：US20080246081A1

公开(公告)日：2008-10-09

申请号：US12015723

申请日：2008-01-17

Applicant: Jian Li ,  Kuo-In Chen ,  Kyle Terril

Inventor： Jian Li ,  Kuo-In Chen ,  Kyle Terril

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66734 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7813

Abstract: A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

Abstract translation: 根据一个实施例的沟槽金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域，设置在漏极区域上方的多个栅极区域，多个栅极绝缘体区域，每个栅极绝缘体区域围绕相应的 所述多个栅极区域中的一个，设置在所述多个栅极绝缘体区域之间的凹入台面中的多个源极区域，设置在所述多个栅极绝缘体区域之间和所述多个源极区域之间的凹入台面中的多个主体区域，以及 漏区。 MOSFET还包括设置在与多个源极区域相邻的每个主体区域中的多个体接触区域，多个源/体接触间隔物，其设置在凹入的台面之上的多个栅极绝缘体区域之间，设置在源极/ 以及多个源/体接触插塞，其设置在源/体接触间隔件之间并将源/体接触件耦合到多个体接触区域和多个源极区域。

公开(公告)号：US20070284754A1

公开(公告)日：2007-12-13

申请号：US11799889

申请日：2007-05-02

Applicant: Ronald Wong ,  Jason Qi ,  Kyle Terrill ,  Kuo-In Chen

Inventor： Ronald Wong ,  Jason Qi ,  Kyle Terrill ,  Kuo-In Chen

IPC: H01L23/532 ,  H01L21/441

CPC classification number: H01L21/76838 ,  H01L21/7684 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Abstract translation: 一种结构包括形成在衬底中的半导体器件; 与半导体器件相邻的绝缘体; 电接触，电耦合到所述半导体器件，其中所述电接触包括钨; 以及耦合到所述电触点的电连接器，其中所述电连接器包括铝。 绝缘体的表面和电接触的表面形成基本均匀的表面。

公开(公告)号：US20050242392A1

公开(公告)日：2005-11-03

申请号：US10836833

申请日：2004-04-30

Applicant: Deva Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Lui ,  Kuo-In Chen ,  Sharon Shi

Inventor： Deva Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Lui ,  Kuo-In Chen ,  Sharon Shi

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/94 ,  H01L21/8238

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Abstract translation: 在沟槽MOSFET中，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。