公开(公告)号：US09887266B2

公开(公告)日：2018-02-06

申请号：US12069712

申请日：2008-02-11

Applicant: The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

Inventor： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

IPC: H01L29/08 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0878 ,  H01L29/167 ,  H01L29/7813

Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.

公开(公告)号：US09685524B2

公开(公告)日：2017-06-20

申请号：US11373630

申请日：2006-03-09

Applicant: The-Tu Chau ,  Hoang Le ,  Kuo-In Chen

Inventor： The-Tu Chau ,  Hoang Le ,  Kuo-In Chen

IPC: H01L29/66

CPC classification number: H01L29/66181

Abstract: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

公开(公告)号：US09437424B2

公开(公告)日：2016-09-06

申请号：US12123664

申请日：2008-05-20

Applicant: Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau

Inventor： Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau

IPC: H01L21/02 ,  H01L29/739 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/02433 ,  H01L21/02516 ,  H01L21/02609 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.

Abstract translation: 高迁移率P沟道功率金属氧化物半导体场效应晶体管。 根据本发明的实施例，制造功率MOSFET，使得空穴沿着沿着（110）晶面的反转/累积通道流动或等效，并且电流在[110]中， 方向或等同物，当负电位相对于源施加到栅极时。 孔的增强的沟道迁移率导致导通状态电阻的沟道部分的减小，从而有利地降低器件的总“导通”电阻。

公开(公告)号：US09412833B2

公开(公告)日：2016-08-09

申请号：US12030809

申请日：2008-02-13

Applicant: The-Tu Chau ,  Hoang Le ,  Kuo-In Chen

Inventor： The-Tu Chau ,  Hoang Le ,  Kuo-In Chen

IPC: H01L29/66

CPC classification number: H01L29/66181

Abstract: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

Abstract translation: 窄半导体沟槽结构的系统和方法。 在第一种方法实施例中，形成窄沟槽的方法包括在衬底上形成绝缘材料的第一层，并通过第一绝缘材料层形成沟槽并进入衬底。 在第一层上形成第二绝缘材料，并且在沟槽的暴露部分上形成第二绝缘材料，并且第二绝缘材料从绝缘材料的第一层和沟槽的底部移除。 沟槽填充有外延材料，并且去除第一绝缘材料层。 通过去除第二绝缘材料的剩余部分形成窄沟槽。

公开(公告)号：US20110053326A1

公开(公告)日：2011-03-03

申请号：US12549190

申请日：2009-08-27

Applicant: Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

Inventor： Yang Gao ,  Kyle Terrill ,  Deva Pattanayak ,  Kuo-In Chen ,  The-Tu Chau ,  Sharon Shi ,  Qufei Chen

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.

Abstract translation: 描述了制造超结沟槽功率MOSFET（金属氧化物半导体场效应晶体管）器件的方法。 超级结中的p型掺杂剂的列通过第一列氧化物与第一列n型掺杂剂与第二列氧化物与第二列n型掺杂剂分离。 在n沟道器件中，用于FET的栅极元件有利地位于p型掺杂剂的列上; 并且在p沟道器件中，用于FET的栅极元件有利地位于n型掺杂剂的列之上。

公开(公告)号：US20110049682A1

公开(公告)日：2011-03-03

申请号：US12873147

申请日：2010-08-31

Applicant: Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

Inventor： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC: H01L29/06 ,  H01L21/203 ,  H01L21/302

CPC classification number: H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Abstract translation: 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。

公开(公告)号：US08409954B2

公开(公告)日：2013-04-02

申请号：US11386927

申请日：2006-03-21

Applicant: The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

Inventor： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattanayak ,  Kyle Terrill ,  Kuo-In Chen

IPC: H01L21/336

CPC classification number: H01L29/0878 ,  H01L29/167 ,  H01L29/7813

Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.

Abstract translation: 超低漏源电阻功率MOSFET。 根据本发明的实施例，半导体器件包括多个沟槽功率MOSFET。 多个沟槽功率MOSFET形成在第二外延层中。 第二外延层形成为与第一外延层相邻并邻接。 第一外延层与高度掺杂有红磷的衬底相邻并邻接地形成。 新型红磷掺杂衬底能够实现所需的低漏源电阻。

公开(公告)号：US20070221989A1

公开(公告)日：2007-09-27

申请号：US11386927

申请日：2006-03-21

Applicant: The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattarayak ,  Kyle Terrill ,  Kuo-In Chen

Inventor： The-Tu Chau ,  Sharon Shi ,  Qufei Chen ,  Martin Hernandez ,  Deva Pattarayak ,  Kyle Terrill ,  Kuo-In Chen

IPC: H01L31/00 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/0878 ,  H01L29/167 ,  H01L29/7813

Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.

Abstract translation: 超低漏源电阻功率MOSFET。 根据本发明的实施例，半导体器件包括多个沟槽功率MOSFET。 多个沟槽功率MOSFET形成在第二外延层中。 第二外延层形成为与第一外延层相邻并邻接。 第一外延层与高度掺杂有红磷的衬底相邻并邻接地形成。 新型红磷掺杂衬底能够实现所需的低漏源电阻。

公开(公告)号：US20070048966A1

公开(公告)日：2007-03-01

申请号：US11373630

申请日：2006-03-09

Applicant: The-Tu Chau ,  Hoang Le ,  Kuo-In Chen

Inventor： The-Tu Chau ,  Hoang Le ,  Kuo-In Chen

IPC: H01L21/76

CPC classification number: H01L29/66181

Abstract: Systems and methods for narrow semiconductor trench structures. In a first method embodiment, a method for forming a narrow trench comprises forming a first layer of insulating material on a substrate and creating a trench through the first layer of insulating material and into the substrate. A second insulating material is formed on the first layer and on exposed portions of the trench and the second insulating material is removed from the first layer of insulating material and the bottom of the trench. The trench is filled with an epitaxial material and the first layer of insulating material is removed. A narrow trench is formed by the removal of remaining portions of the second insulating material.

Abstract translation: 窄半导体沟槽结构的系统和方法。 在第一种方法实施例中，形成窄沟槽的方法包括在衬底上形成绝缘材料的第一层，并通过第一绝缘材料层形成沟槽并进入衬底。 在第一层上形成第二绝缘材料，并且在沟槽的暴露部分上形成第二绝缘材料，并且第二绝缘材料从第一绝缘材料层和沟槽的底部移除。 沟槽填充有外延材料，并且去除第一绝缘材料层。 通过去除第二绝缘材料的剩余部分形成窄沟槽。

公开(公告)号：US09230810B2

公开(公告)日：2016-01-05

申请号：US12873147

申请日：2010-08-31

Applicant: Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

Inventor： Hamilton Lu ,  The-Tu Chau ,  Kyle Terrill ,  Deva N. Pattanayak ,  Sharon Shi ,  Kuo-In Chen ,  Robert Xu

IPC: H01L21/322 ,  H01L21/20 ,  H01L21/22 ,  H01L29/78

CPC classification number: H01L21/2205 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/02694 ,  H01L29/16 ,  H01L29/365 ,  H01L29/7813

Abstract: Systems and methods for substrate wafer back side and edge cross section seals. In accordance with a first method embodiment, a silicon wafer of a first conductivity type is accessed. An epitaxial layer of the first conductivity type is grown on a front surface of the silicon wafer. The epitaxial layer is implanted to form a region of an opposite conductivity type. The growing and implanting are repeated to form a vertical column of the opposite conductivity type. The wafer may also be implanted to form a region of the opposite conductivity type vertically aligned with the vertical column.

Abstract translation: 衬底晶圆背面和边缘截面密封的系统和方法。 根据第一方法实施例，访问第一导电类型的硅晶片。 第一导电类型的外延层生长在硅晶片的前表面上。 植入外延层以形成相反导电类型的区域。 重复生长和植入以形成相反导电类型的垂直柱。 也可以将晶片植入以形成与垂直柱垂直对准的相反导电类型的区域。