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    Passivation layer for semiconductor devices
    4.
    发明授权
    Passivation layer for semiconductor devices 有权
    半导体器件钝化层

    公开(公告)号：US08643151B2

    公开(公告)日：2014-02-04

    申请号：US13036897

    申请日：2011-02-28

    申请人： Jen-Hao Liu ,  Chyi-Tsong Ni ,  Hsiao-Yin Lin ,  Chung-Min Lin

    发明人： Jen-Hao Liu ,  Chyi-Tsong Ni ,  Hsiao-Yin Lin ,  Chung-Min Lin

    IPC分类号： H01L23/58

    CPC分类号： H01L23/3192 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.

    摘要翻译： 本公开的实施例提供一种半导体器件。 半导体器件包括多个金属化层，其包括最上面的金属化层。 最上面的金属化层具有两个具有厚度T1并被间隙隔开的金属特征。 复合钝化层包括氮化物层下的HDP CVD氧化物层。 复合钝化层设置在金属特征上并部分填充间隙。 复合钝化层的厚度T2约为厚度T1的20％至50％。

    Low temperature method for minimizing copper hillock defects
    7.
    发明申请
    Low temperature method for minimizing copper hillock defects 有权
    用于最小化铜小丘缺陷的低温方法

    公开(公告)号：US20060252258A1

    公开(公告)日：2006-11-09

    申请号：US11122393

    申请日：2005-05-05

    申请人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    发明人： Jun Wu ,  Wen-Long Lee ,  Chyi-Tsong Ni ,  Shih-Chi Lin

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/76801 ,  H01L21/76883

    摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200 ° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

    摘要翻译： 公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。 低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。 小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。 在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

    Method of fabricating A1N anti-reflection coating on metal layer
    9.
    发明授权
    Method of fabricating A1N anti-reflection coating on metal layer 失效
    在金属层上制造AlN防反射涂层的方法

    公开(公告)号：US6017816A

    公开(公告)日：2000-01-25

    申请号：US805295

    申请日：1997-02-25

    申请人： Chyi-Tsong Ni ,  Kuei-Chang Tsai

    发明人： Chyi-Tsong Ni ,  Kuei-Chang Tsai

    IPC分类号： H01L21/027 ,  H01L21/285 ,  H01L21/318 ,  H01L21/3213 ,  H01L21/4763

    CPC分类号： H01L21/32139 ,  H01L21/0276 ,  H01L21/28568 ,  H01L21/318 ,  H01L21/32137 ,  Y10S438/907 ,  Y10S438/913 ,  Y10S438/952

    摘要： A method of fabricating notching free metal interconnection lines by utilizing aluminum nitride (AlN) as an anti-reflection coating. First, field oxide regions are formed on a semiconductor silicon wafer. Then, electrical element structures such as transistor, capacitor and resistor are formed on the predetermined area. Next, a barrier layer, a metal layer and an anti-reflection layer are successively deposited overlaying the entire silicon wafer surface. Next, the photoresist pattern is formed by the conventional lithography technique. By using photoresist pattern as an etching protection mask, the barrier layer, metal layer and anti-reflection layer are also patterned to form metal interconnection lines. Thereafter, the photoresist is stripped by oxygen plasma and sulfuric acid.

    摘要翻译： 一种通过利用氮化铝（AlN）作为抗反射涂层来制造无缝金属互连线的方法。 首先，在半导体硅晶片上形成场氧化物区域。 然后，在预定区域上形成诸如晶体管，电容器和电阻器的电气元件结构。 接下来，在整个硅晶片表面上依次沉积阻挡层，金属层和抗反射层。 接下来，通过常规的光刻技术形成光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻保护掩模，阻挡层，金属层和抗反射层也被图案化以形成金属互连线。 此后，通过氧等离子体和硫酸剥离光致抗蚀剂。