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    SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING
    1.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING 有权
    半导体封装，包括通过开放的半导体芯片

    公开(公告)号：US20130105988A1

    公开(公告)日：2013-05-02

    申请号：US13533473

    申请日：2012-06-26

    申请人： Chang-Cheol LEE ,  Hyun-Jun KIM ,  In-Young LEE ,  Ki-Kwon JEONG

    发明人： Chang-Cheol LEE ,  Hyun-Jun KIM ,  In-Young LEE ,  Ki-Kwon JEONG

    IPC分类号： H01L23/48

    CPC分类号： H01L23/13 ,  H01L21/565 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1815

    摘要： A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

    摘要翻译： 半导体封装包括具有通过其形成的第一开口的衬底，以倒装芯片方式堆叠在衬底上并具有穿过其中的第二开口的第一半导体芯片，以倒装芯片方式堆叠在第一半导体芯片上的第二半导体芯片，以及 具有通过其形成的第三开口，以及覆盖所述第一半导体芯片和所述第二半导体芯片并填充所述基板和所述第一半导体芯片之间的空间的模塑材料，所述第一半导体芯片和所述第二半导体芯片之间的空间，以及填充 第一开口，第二开口和第三开口中的每一个。

    Semiconductor package including semiconductor chip with through opening
    6.
    发明授权
    Semiconductor package including semiconductor chip with through opening 有权
    半导体封装包括半导体芯片通过开口

    公开(公告)号：US08941245B2

    公开(公告)日：2015-01-27

    申请号：US13533473

    申请日：2012-06-26

    申请人： Chang-Cheol Lee ,  Hyun-Jun Kim ,  In-Young Lee ,  Ki-Kwon Jeong

    发明人： Chang-Cheol Lee ,  Hyun-Jun Kim ,  In-Young Lee ,  Ki-Kwon Jeong

    IPC分类号： H01L23/52 ,  H01L23/13 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56

    CPC分类号： H01L23/13 ,  H01L21/565 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1815

    摘要： A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

    摘要翻译： 半导体封装包括具有通过其形成的第一开口的衬底，以倒装芯片方式堆叠在衬底上并具有穿过其中的第二开口的第一半导体芯片，以倒装芯片方式堆叠在第一半导体芯片上的第二半导体芯片，以及 具有通过其形成的第三开口，以及覆盖所述第一半导体芯片和所述第二半导体芯片并填充所述基板和所述第一半导体芯片之间的空间的模塑材料，所述第一半导体芯片和所述第二半导体芯片之间的空间，以及填充 第一开口，第二开口和第三开口中的每一个。

    Device and method for manufacturing wafer-level package
    9.
    发明申请
    Device and method for manufacturing wafer-level package 审中-公开
    晶圆级封装制造装置及方法

    公开(公告)号：US20060105477A1

    公开(公告)日：2006-05-18

    申请号：US11280838

    申请日：2005-11-15

    申请人： Suk-Kun Lim ,  Chae-Hun Im ,  Min-Ill Kim ,  Chang-Cheol Lee

    发明人： Suk-Kun Lim ,  Chae-Hun Im ,  Min-Ill Kim ,  Chang-Cheol Lee

    IPC分类号： H01L21/66 ,  G01R31/26

    CPC分类号： H01L21/67271 ,  G01R31/2893 ,  H01L21/67144

    摘要： In an embodiment of the invention, a device for manufacturing a wafer-level package includes a wafer sawing unit, a sorting unit, a pickup unit, and a placing unit. The wafer sawing unit cuts a wafer into wafer-level packages. The sorting unit performs a sorting process on the wafer-level packages to judge whether each of the wafer-level packages is normal or not. The pickup unit picks up the normal wafer-level packages. The placing unit stores the normal wafer-level packages in a storage case. The sawing process, the sorting process, and the placing process for the wafer-level package can be automatically performed within one device, thus a processing time reduction, a processing accuracy increase, and manpower reduction are achieved compared with the case where the processes are performed manually.

    摘要翻译： 在本发明的一个实施例中，用于制造晶片级封装的器件包括晶片锯切单元，分类单元，拾取单元和放置单元。 晶圆锯切单元将晶片切割成晶片级封装。 分选单元对晶片级封装执行分类处理，以判断晶片级封装是否正常。 拾取单元拾取正常晶圆级封装。 放置单元将正常的晶片级封装存储在存储盒中。 可以在一个设备内自动执行晶片级封装的锯切过程，分选过程和放置过程，从而与处理的情况相比，实现了处理时间缩短，处理精度提高和人力减少 手动执行。

    Multi-chip package
    10.
    发明授权
    Multi-chip package 有权
    多芯片封装

    公开(公告)号：US6087722A

    公开(公告)日：2000-07-11

    申请号：US291913

    申请日：1999-04-14

    申请人： Kwan Jai Lee ,  Young Jae Song ,  Do Soo Jeong ,  Tae Je Cho ,  Suk Hong Chang ,  Chang Cheol Lee ,  Beung Seuck Song ,  Jong Hee Choi

    发明人： Kwan Jai Lee ,  Young Jae Song ,  Do Soo Jeong ,  Tae Je Cho ,  Suk Hong Chang ,  Chang Cheol Lee ,  Beung Seuck Song ,  Jong Hee Choi

    IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L23/48

    CPC分类号： H01L23/49575 ,  H01L23/4951 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181

    摘要： A multi-chip stack package does not include a die pad. The elimination of the die pad provides more room for elements in the package which. Thus, a balanced inner package structure can be achieved, and a poor molding which may expose one of the package elements can be avoided. In the package, an upper chip is bonded to the top surface of a lower chip. To stabilize the chips, auxiliary or inner leads of a lead frame attach to the top surface of a lower chip. This shortens wire lengths between the chips and the inner leads. The shorter wires reduce wire loop heights and thus reduce the probability of exposing wires in a subsequent transfer-molding. A multi-chip stack package which includes an auxiliary lead(s) is also disclosed. The auxiliary leads attach to the top surface of the lower chip and can provide a stable support of a semiconductor chip and prevent the chip from tilting and shifting in transfer-molding. An auxiliary lead can be between the lower and upper chips. The auxiliary leads can also be positioned to prevent undesirable spreading of an adhesive when an upper chip is attached to a lower chip.

    摘要翻译： 多芯片堆叠封装不包括管芯焊盘。 消除管芯垫为封装中的元件提供了更多的空间。 因此，可以实现平衡的内包装结构，并且可以避免可能暴露包装元件之一的不良成型。 在封装中，上芯片结合到下芯片的顶表面。 为了稳定芯片，引线框架的辅助引线或内引线连接到下芯片的顶表面。 这缩短了芯片和内部引线之间的电线长度。 较短的电线可以降低电线回路高度，从而降低在随后的传递模塑中暴露电线的可能性。 还公开了一种包括辅助引线的多芯片堆叠封装。 辅助引线连接到下芯片的顶表面，并且可以提供半导体芯片的稳定支撑，并防止芯片在传递成型中倾斜和移位。 辅助引线可以在下部和上部芯片之间。 辅助引线也可以被定位以防止当上芯片附接到下芯片时粘合剂的不希望的扩散。