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公开(公告)号：US11700004B2
公开(公告)日：2023-07-11
申请号：US17587914
申请日：2022-01-28
发明人： HaiFeng Zhou
CPC分类号： H03K23/005 , H03M7/16
摘要： A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.
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公开(公告)号：US11494192B2
公开(公告)日：2022-11-08
申请号：US16860842
申请日：2020-04-28
发明人： Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
摘要： A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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公开(公告)号：US20220196487A1
公开(公告)日：2022-06-23
申请号：US17126326
申请日：2020-12-18
发明人： Lin WANG
摘要： A current control module is employed to protect a conductive feature of a printed circuit board (PCB) from an overcurrent event by comparing a reference voltage output from a compensation circuit connected to a reference power supply to a voltage output from a conductive feature connected to a power supply which is different from the reference power supply. The reference output voltage is representative of an anticipated voltage output from the conductive feature. The current control module is configured to initiate regulation of power to the conductive feature when the voltage output from the conductive feature exceeds the reference voltage output.
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公开(公告)号：US10656951B2
公开(公告)日：2020-05-19
申请号：US15789318
申请日：2017-10-20
发明人： Jiasheng Chen , YunXiao Zou , Bin He , Angel E. Socarras , QingCheng Wang , Wei Yuan , Michael Mantor
摘要： A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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公开(公告)号：US20180113731A1
公开(公告)日：2018-04-26
申请号：US15348225
申请日：2016-11-10
发明人： Jeffrey G. Cheng , Yinan Jiang , Guangwen Yang , Kelly Donald Clark Zytaruk , LingFei Liu , XiaoWei Wang
CPC分类号： G06F9/45558 , G06F2009/4557 , G06F2009/45575 , G06T1/20
摘要： A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.
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公开(公告)号：US20180113714A1
公开(公告)日：2018-04-26
申请号：US15789318
申请日：2017-10-20
发明人： Jiasheng CHEN , YunXiao ZOU , Bin HE , Angel E. SOCARRAS , QingCheng WANG , Wei YUAN , Michael MANTOR
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3869 , G06F9/3885 , G06F15/80 , G06F2015/768
摘要： A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
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公开(公告)号：US11342922B1
公开(公告)日：2022-05-24
申请号：US17129349
申请日：2020-12-21
发明人： HaiFeng Zhou
摘要： A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.
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公开(公告)号：US09870969B2
公开(公告)日：2018-01-16
申请号：US14193462
申请日：2014-02-28
发明人： I-Tseng Lee , Yu-Ling Hsieh
CPC分类号： H01L23/13 , H01L2224/16225 , H01L2924/0002 , H01L2924/01078 , H05K1/024 , H05K1/036 , H05K3/0052 , H05K3/0061 , H05K3/3452 , H05K2201/0209 , H05K2201/0959 , H05K2201/10674 , H01L2924/00
摘要： The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
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公开(公告)号：US09214438B2
公开(公告)日：2015-12-15
申请号：US14633205
申请日：2015-02-27
发明人： I-Tseng Lee , Yi Hsiu Liu
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48 , H01L23/00 , H01L25/065
CPC分类号： H01L24/17 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/1134 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/1356 , H01L2224/16113 , H01L2224/16221 , H01L2224/16225 , H01L2224/16227 , H01L2224/17134 , H01L2224/17179 , H01L2224/17515 , H01L2224/17517 , H01L2224/26125 , H01L2224/26155 , H01L2224/29011 , H01L2224/29012 , H01L2224/29019 , H01L2224/2919 , H01L2224/3201 , H01L2224/32057 , H01L2224/32058 , H01L2224/32059 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81193 , H01L2224/83191 , H01L2224/83193 , H01L2225/06513 , H01L2225/06565 , H01L2924/07025 , H01L2924/15311 , H01L2924/351 , H01L2924/3512 , H01L2924/00014 , H01L2924/00 , H01L2924/014 , H01L2924/00012
摘要： The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer. The structure and method of present invention at least provide more strength and stress buffer to resist die warpage and absorb thermal cycling stress, and then prevents the bump and dielectric materials in the die-die stacking structure from cracking caused by thermal stress or external mechanical stress.
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公开(公告)号：US20140246223A1
公开(公告)日：2014-09-04
申请号：US14193462
申请日：2014-02-28
发明人： I-Tseng Lee , Yu-Ling Hsieh
IPC分类号： H05K1/02
CPC分类号： H01L23/13 , H01L2224/16225 , H01L2924/0002 , H01L2924/01078 , H05K1/024 , H05K1/036 , H05K3/0052 , H05K3/0061 , H05K3/3452 , H05K2201/0209 , H05K2201/0959 , H05K2201/10674 , H01L2924/00
摘要： The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
摘要翻译： 本发明涉及一种包括堆积物和设置在积聚物上的阻焊层的基材。 阻焊层具有背离堆积物的上表面。 阻焊层在其上表面具有多个槽。 阻焊层的凹槽可以更好地消除或减轻由热引起的大的阻焊剂区域上积累的应力和/或材料的基板的热膨胀失配系数，从而可以防止和减少基板或封装的翘曲。
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