公开(公告)号：US12130184B2

公开(公告)日：2024-10-29

申请号：US17617213

申请日：2020-06-16

申请人： Ircon Drying Systems AB

发明人： Fredrik Liljesater

IPC分类号： G01J5/04 ,  D21F5/06 ,  D21F7/00 ,  G01J5/00 ,  G01J5/06 ,  D21G1/00

CPC分类号： G01J5/048 ,  D21F7/00 ,  G01J5/0022 ,  G01J5/064 ,  D21F5/06 ,  D21G1/0073 ,  G01J2005/0029

摘要： The present invention relates to an arrangement (1) for measuring the temperature of a web. The arrangement (1) comprises a plurality of sensors (3) for contactless measuring of the temperature, an elongated housing (5) intended for extending essentially along a transverse direction (T) which is transverse to the direction of movement of a web. The sensors (3) are arranged in a chamber (6) within the housing (5) and spread along the front side (7a) of the housing (5). Each sensor (3) is connected to a data bus (9) for providing information of the measured temperature to other systems and/or apparatuses. The sensors (3) are attached to a support structure (19) having at least one rotatable shaft (23) in the interior of the housing (7), and wherein the shaft (23) is arranged to rotate the support structure (19) such that the sensors (3) are displaced to a calibration and/or protection position away from the openings (11) for calibration and/or protection of the sensors (3). The invention also relates to a method for measuring the temperature of a web, a computer program, a computer readable medium and a control unit.

公开(公告)号：US12124247B2

公开(公告)日：2024-10-22

申请号：US17465305

申请日：2021-09-02

申请人： SanDisk Technologies LLC

发明人： Fei Zhou ,  Cheng-Chung Chu ,  Raghuveer Makala

IPC分类号： G05B19/418 ,  G05B13/02 ,  H01L21/66

CPC分类号： G05B19/41875 ,  G05B13/027 ,  H01L22/20 ,  G05B2219/32335 ,  G05B2219/32368 ,  G05B2219/45031

摘要： Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).

公开(公告)号：US12121732B2

公开(公告)日：2024-10-22

申请号：US17897041

申请日：2022-08-26

申请人： Pacesetter, Inc.

发明人： Chunlan Jiang ,  Gene A. Bornzin

IPC分类号： A61N1/37 ,  A61N1/365 ,  A61N1/372 ,  A61N1/375 ,  A61N1/39

CPC分类号： A61N1/3714 ,  A61N1/36535 ,  A61N1/37258 ,  A61N1/37264 ,  A61N1/37512 ,  A61N1/39622

摘要： For use by an implantable system including a first and second leadless pacemakers (LPs) implanted, respectively, in first and second cardiac chambers, a method comprises storing, within memory of the first LP, a paced activation morphology template corresponding to far-field signal components expected to be present in an EGM sensed by the first LP when a pacing pulse delivered to the second cardiac chamber by the second LP captures the second cardiac chamber. The method also includes the first LP comparing a morphology of a portion of an EGM sensed by the first LP to the paced activation morphology template to determine whether a match therebetween is detected, and determining whether capture of the second cardiac chamber occurred or failed to occur, based on whether the first LP detects a match between the morphology of the portion of the EGM and the paced activation morphology template.

公开(公告)号：US12112814B2

公开(公告)日：2024-10-08

申请号：US17837345

申请日：2022-06-10

申请人： Western Digital Technologies, Inc.

发明人： Ke Zhang ,  Ming Wang ,  Liang Li

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

摘要： Technology for open block boundary group programming of non-volatile memory such as NAND. The open block boundary group could potentially be read in response to a request from a host for the data stored in the group. In an aspect, the memory system will determine whether programming a group of memory cells in a selected block will result in an open block. If it will not result in an open block, then the memory system uses a first set of programming parameters to program the group. However, if it will result in an open block then the memory system uses a second set of programming parameters to program the boundary group. The programming parameters may include verify levels and/or a program voltage step size. The second set of programming parameters can tighten Vt distributions, which mitigates mis-reads if the boundary group is read.

公开(公告)号：US12102830B2

公开(公告)日：2024-10-01

申请号：US18319346

申请日：2023-05-17

申请人： Pacesetter, Inc.

发明人： Paul Paspa ,  Thomas B. Eby ,  Matthew G. Fishler ,  Carl Lance Boling ,  Thomas Robert Luhrs ,  Russell Klehn ,  Tyler J. Strang ,  Arees Garabed ,  Kavous Sahabi ,  Brett Villavicencio ,  Wes Alleman ,  Alex Soriano ,  Matthew R. Malone ,  Conor P. Foley

IPC分类号： A61N1/362 ,  A61N1/05 ,  A61N1/375

CPC分类号： A61N1/3629 ,  A61N1/0568 ,  A61N1/0573 ,  A61N1/0575 ,  A61N1/37512 ,  A61N1/37518 ,  A61N1/3754

摘要： A leadless biostimulator has a housing including an electronics compartment, an electronics assembly mounted in the electronics compartment, a proximal electrode that disposed on and/or integrated into the housing, and an electrical feedthrough assembly. The electrical feedthrough assembly includes a distal electrode and a flange. The flange is mounted on the housing. The distal electrode is electrically isolated from the flange by an insulator and configured to be placed in contact with target tissue to which a pacing impulse is to be transmitted by the leadless biostimulator. A mount is mounted on the flange and thereby mounted on the electrical feedthrough assembly. A fixation element is mounted on the mount and configured to facilitate fixation of the leadless biostimulator to tissue of a patient.

公开(公告)号：US12099743B2

公开(公告)日：2024-09-24

申请号：US17709745

申请日：2022-03-31

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Liang Li ,  Loc Tu ,  Yinfeng Yu ,  Xuan Tian

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06N5/04

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06N5/04

摘要： A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.

公开(公告)号：US12079496B2

公开(公告)日：2024-09-03

申请号：US17901310

申请日：2022-09-01

申请人： SanDisk Technologies LLC

发明人： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC分类号： G06F3/06

CPC分类号： G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

摘要： Technology is disclosed herein for managing timing parameters when programming memory cells. Timing parameters used sub-clocks in an MLC program mode may also be used for those same sub-clocks in a first SLC program mode. However, in a second SLC program mode a different set of timing parameters may be used for that set of sub-clocks. Using the same set of timing parameters for the MLC program mode and the first SLC program mode saves storage space. However, the timing parameters for the MLC program mode may be slower than desired for SLC programming. A different set of timing parameters may be used for the second SLC program mode to provide for faster program operation. Moreover, the different set of timing parameters used for the faster SLC program mode do not require storage of a separate set of timing parameters.

公开(公告)号：US12033958B2

公开(公告)日：2024-07-09

申请号：US17536800

申请日：2021-11-29

申请人： WESTERN DIGITAL TECHNOLOGIES, INC.

发明人： Yangming Liu ,  Shenghua Huang ,  Bo Yang ,  Ning Ye ,  Cong Zhang

IPC分类号： H01L23/00 ,  H01L23/552 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/552 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/3511

摘要： A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.

公开(公告)号：US12033377B2

公开(公告)日：2024-07-09

申请号：US17696707

申请日：2022-03-16

申请人： Maxar Space LLC

发明人： Manuel Gonzalez-Rivero ,  David R. Herdzik ,  Jonathan C. Harris

IPC分类号： G06V10/82 ,  G06N3/048 ,  G06V10/774 ,  G06N3/08 ,  G06T3/4046 ,  G06T7/10 ,  G06V10/75 ,  G06V30/18

CPC分类号： G06V10/82 ,  G06N3/048 ,  G06V10/7747 ,  G06N3/08 ,  G06T3/4046 ,  G06T7/10 ,  G06V10/751 ,  G06V30/18086

摘要： Methods and structures are presented for implementing an automatic target recognition system as a convolutional neural network (CNN) in a satellite or other environment with constrained resources, such as limited memory capacity and limited processing capability. For example, this allows for the automatic target recognition to be implemented on a field programmable gate array (FPGA). Image data is split into subsets of contiguous pixels, with the subsets processed in parallel in a CNN of a corresponding processing node using quantized weight values that are determined in a training process that accounts for the constraints of the automatic target recognition system. The results of the automatic target recognition process is based on the combined output of the processing nodes.

公开(公告)号：US12032837B2

公开(公告)日：2024-07-09

申请号：US17957424

申请日：2022-09-30

申请人： SanDisk Technologies LLC

发明人： Yuki Mizutani ,  Kazutaka Yoshizawa ,  Kiyokazu Shishido ,  Eiichi Fujikura

IPC分类号： G06F3/06

CPC分类号： G06F3/0626 ,  G06F3/0629 ,  G06F3/0679

摘要： A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.