公开(公告)号：US12124616B2

公开(公告)日：2024-10-22

申请号：US17830225

申请日：2022-06-01

申请人： Intel Corporation

发明人： Claire Vishik ,  Reshma Lal ,  Santosh Ghosh

IPC分类号： G06F21/64 ,  G06F16/14 ,  G06F21/60

CPC分类号： G06F21/64 ,  G06F21/602 ,  G06F16/152

摘要： A system and method of enhancing the trustworthiness of an artificial intelligence system include detecting whether a data element includes an existing data domain tag, processing the data element into a transformed data element, generating a data domain tag, where the data domain tag includes at least a data domain identifier and a timestamp, appending the data domain tag to the transformed data element, creating a signature for the transformed data element and the appended data domain tag using a private key, and creating another signature for the data domain tag using the private key.

公开(公告)号：US12112055B2

公开(公告)日：2024-10-08

申请号：US16865566

申请日：2020-05-04

申请人： Intel Corporation

发明人： Piotr Wysocki ,  Sanjeev N. Trika ,  Gregory B. Tucker ,  Jackson Ellis ,  Jonathan M. Hughes

IPC分类号： G06F3/06 ,  G06F9/30

CPC分类号： G06F3/0652 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688 ,  G06F9/30029

摘要： An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.

公开(公告)号：US12106457B2

公开(公告)日：2024-10-01

申请号：US18460350

申请日：2023-09-01

申请人： Intel Corporation

发明人： Daniel Pohl

IPC分类号： G06T5/80 ,  G02B27/01 ,  G06T5/50

CPC分类号： G06T5/80 ,  G02B27/0172 ,  G06T5/50 ,  G02B2027/011 ,  G06T2207/10016 ,  G06T2207/10024 ,  G06T2207/20221

摘要： Described herein is a technique in which a plurality of distortion meshes compensate for radial and chromatic aberrations created by optical lenses. The plurality of distortion meshes may include different lens specific parameters that allow the distortion meshes to compensate for chromatic aberrations created within received images. The plurality of distortion meshes may correspond to a red color channel, green color channel, or blue color channel to compensate for the chromatic aberrations. The distortion meshes may also include shaped distortions and grids to compensate for radial distortions, such as pin cushion distortions. In one example, the system uses a barrel-shaped distortion and a triangulation grid to compensate for the distortions created when the received image is displayed on a lens.

公开(公告)号：US12094048B2

公开(公告)日：2024-09-17

申请号：US17497618

申请日：2021-10-08

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Arthur Hunter ,  Kamal Sinha ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma

IPC分类号： G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T17/20

CPC分类号： G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T17/20

摘要： Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：US12086205B2

公开(公告)日：2024-09-10

申请号：US17211627

申请日：2021-03-24

申请人： Intel Corporation

发明人： Chunhui Mei ,  Hong Jiang ,  Jiasheng Chen ,  Yongsheng Liu ,  Yan Li

IPC分类号： G06F17/16 ,  G06F7/544 ,  G06F9/30 ,  G06F15/80 ,  G06F17/11

CPC分类号： G06F17/16 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30043 ,  G06F15/8046 ,  G06F17/11

摘要： Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.

公开(公告)号：US12067641B2

公开(公告)日：2024-08-20

申请号：US17749266

申请日：2022-05-20

申请人： Intel Corporation

发明人： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC分类号： G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

CPC分类号： G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

摘要： One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

公开(公告)号：US12066975B2

公开(公告)日：2024-08-20

申请号：US17429291

申请日：2020-03-14

申请人： Intel Corporation

发明人： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  K Pattabhiraman ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  S Jayakrishna P ,  Prasoonkumar Surti

IPC分类号： G06F12/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC分类号： G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

摘要： Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：US12056789B2

公开(公告)日：2024-08-06

申请号：US18455128

申请日：2023-08-24

申请人： Intel Corporation

发明人： Naveen Matam ,  Lance Cheney ,  Eric Finley ,  Varghese George ,  Sanjeev Jahagirdar ,  Altug Koker ,  Josh Mastronarde ,  Iqbal Rajwani ,  Lakshminarayanan Striramassarma ,  Melaku Teshome ,  Vikranth Vemulapalli ,  Binoj Xavier

IPC分类号： G06T1/20 ,  G06F13/40

CPC分类号： G06T1/20 ,  G06F13/4027

摘要： Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：US12052368B2

公开(公告)日：2024-07-30

申请号：US17133166

申请日：2020-12-23

申请人： Intel Corporation

发明人： Ravi L. Sahita ,  Travis T. Schluessler

IPC分类号： H04L9/32 ,  G06F9/455 ,  G06F12/14 ,  G06F21/53 ,  G06F21/72

CPC分类号： H04L9/3234 ,  G06F9/45558 ,  G06F12/1433 ,  G06F12/1491 ,  G06F21/53 ,  G06F21/72 ,  G06F2009/45587 ,  G06F2221/034 ,  G06F2221/2149 ,  G06F2221/2153

摘要： A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.

公开(公告)号：US12052287B2

公开(公告)日：2024-07-30

申请号：US17683919

申请日：2022-03-01

申请人： Fortinet, Inc.

发明人： Shushan Wen ,  John Cortes ,  Zhi Guo

IPC分类号： H04L9/40

CPC分类号： H04L63/20 ,  H04L63/0236 ,  H04L63/104

摘要： Systems, devices, and methods are discussed for classifying a number of security policies in relation to criteria for applying those security policies to yield a dual bitmap scheme representing a correlation between security policies and one or more criteria.