公开(公告)号：US11233053B2

公开(公告)日：2022-01-25

申请号：US16643827

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

摘要： A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11227829B2

公开(公告)日：2022-01-18

申请号：US15940531

申请日：2018-03-29

申请人： Intel Corporation

发明人： Sairam Subramanian ,  Walid M. Hafez

IPC分类号： H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234

摘要： Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.

公开(公告)号：US11222982B2

公开(公告)日：2022-01-11

申请号：US16321356

申请日：2016-09-29

申请人： Intel Corporation

发明人： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC分类号： H01L21/8258 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20

摘要： Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

公开(公告)号：US11201114B2

公开(公告)日：2021-12-14

申请号：US16465119

申请日：2016-12-29

申请人： Intel Corporation

发明人： Kevin Lin ,  Christopher J. Jezewski ,  Richard F. Vreeland ,  Tristan A. Tronic

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L27/01 ,  H01L49/02

摘要： Methods/structures of forming thin film resistors using interconnect liner materials are described. Those methods/structures may include forming a first liner in a first trench, wherein the first trench is disposed in a dielectric layer that is disposed on a substrate. Forming a second liner in a second trench, wherein the second trench is adjacent the first trench, forming an interconnect material on the first liner in the first trench, adjusting a resistance value of the second liner, forming a first contact structure on a top surface of the interconnect material, and forming a second contact structure on the second liner.

公开(公告)号：US11195932B2

公开(公告)日：2021-12-07

申请号：US16650824

申请日：2017-12-29

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Brian S. Doyle ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov

IPC分类号： H01L29/51 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

摘要： In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device.

公开(公告)号：US11171233B2

公开(公告)日：2021-11-09

申请号：US16490502

申请日：2017-03-31

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/66

摘要： Disclosed are systems, methods, and apparatus directed to the fabrication of vertical field effect transistors (VFETs) and VFETs with self-aligned wordlines. In one embodiment, the source and/or drain of the VFETs can include n-doped silicon. In one embodiment, the VFETs can include a channel that can be made of intrinsic silicon. In one embodiment, the source, drain, and/or channel can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD), and the like. In one embodiment, an STI process can be used to fabricate one or more recesses, which can reach the drains of the VFETs. In one embodiment, the systems, methods, and apparatus can permit the self-alignment of one or more wordlines of the VFETs with the one or more fins, and/or gate metals and gate materials of the VFETs.

公开(公告)号：US11171043B2

公开(公告)日：2021-11-09

申请号：US16329172

申请日：2016-09-30

申请人： Intel Corporation

发明人： Charles H. Wallace ,  Marvin Y. Paik ,  Hyunsoo Park ,  Mohit K. Haran ,  Alexander F. Kaplan ,  Ruth A. Brain

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

摘要： Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.

公开(公告)号：US11164790B2

公开(公告)日：2021-11-02

申请号：US16632319

申请日：2017-08-17

申请人： Intel Corporation

发明人： Leonard P Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L27/088

摘要： Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US11145739B2

公开(公告)日：2021-10-12

申请号：US16075953

申请日：2016-03-04

申请人： Intel Corporation

发明人： Gilbert W. Dewey ,  Rafael Rios ,  Van H. Le ,  Jack T. Kavalieros

IPC分类号： H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L21/465 ,  H01L29/267

摘要： FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

公开(公告)号：US11139151B1

公开(公告)日：2021-10-05

申请号：US15922762

申请日：2018-03-15

申请人： Intel Corporation

发明人： Patrick Whiting ,  Jeffrey L. Young ,  Ryan Wood ,  Eric Scott ,  David Laube ,  Alex Collins

IPC分类号： H01L21/3065 ,  B08B7/00 ,  H01J37/32

摘要： A method is disclosed, which comprises estimating a first value of a parameter of a component, prior to a use of the component in a reactor. In an example, the parameter of the component is to change during the use of the component in the reactor. The component may be treated, subsequent to the use of the component in the reactor. A second value of the parameter of the component may be estimated, subsequent to treating the component. The second value may be compared with the first value, where a reuse of the component in the reactor is to occur in response to the second value being within a threshold range of the first value.