Invention Grant
- Patent Title: Integrated nanowire and nanoribbon patterning in transistor manufacture
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Application No.: US16632319Application Date: 2017-08-17
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Publication No.: US11164790B2Publication Date: 2021-11-02
- Inventor: Leonard P Guler , Biswajeet Guha , Mark Armstrong , Tahir Ghani , William Hsu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2017/047409 WO 20170817
- International Announcement: WO2019/035837 WO 20190221
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/308 ; H01L27/088

Abstract:
Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).
Public/Granted literature
- US20200176321A1 INTEGRATED NANOWIRE & NANORIBBON PATTERNING IN TRANSISTOR MANUFACTURE Public/Granted day:2020-06-04
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