公开(公告)号：US09916988B2

公开(公告)日：2018-03-13

申请号：US14914627

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Shakuntala Sundararajan ,  Nadia Rahhal-Orabi ,  Leonard P Guler ,  Michael Harper ,  Ralph Thomas Troeger

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/31051 ,  H01L21/76814 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/401

Abstract: Techniques and structures for protecting etched features during etch mask removal. In embodiments, a mask is patterned and a substrate layer etched to transfer the pattern. Subsequent to etching the substrate layer, features patterned into the substrate are covered with a sacrificial material backfilling the etch mask. At least a top portion of the mask is removed with the substrate features protected by the sacrificial material. The sacrificial material and any remaining portion of the mask are then removed. In further embodiments, a gate contact opening etched into a substrate layer is protected with a sacrificial material having the same composition as a first material layer of a multi-layered etch mask. A second material layer of the etch mask having a similar composition as the substrate layer is removed before subsequently removing the sacrificial material concurrently with the first mask material layer.

公开(公告)号：US11164790B2

公开(公告)日：2021-11-02

申请号：US16632319

申请日：2017-08-17

Applicant: Intel Corporation

Inventor： Leonard P Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).