Invention Grant
- Patent Title: Field effect transistors with a gated oxide semiconductor source/drain spacer
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Application No.: US16075953Application Date: 2016-03-04
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Publication No.: US11145739B2Publication Date: 2021-10-12
- Inventor: Gilbert W. Dewey , Rafael Rios , Van H. Le , Jack T. Kavalieros
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2016/021039 WO 20160304
- International Announcement: WO2017/151148 WO 20170908
- Main IPC: H01L29/49
- IPC: H01L29/49 ; H01L29/66 ; H01L29/417 ; H01L21/8234 ; H01L21/02 ; H01L27/092 ; H01L21/465 ; H01L29/267

Abstract:
FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.
Public/Granted literature
- US20210193814A1 FIELD EFFECT TRANSISTORS WITH A GATED OXIDE SEMICONDUCTOR SOURCE/DRAIN SPACER Public/Granted day:2021-06-24
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